AD7794

Preliminary Technical Data

REV.PrE 6/04 | Page 18

A fullscale calibration is required each time the gain of a channel is changed.

1

1

0

System Offset Calibration.

User should connect the system zero-scale input to the .channel input pins as selected by the CH2-CH0 bits.

A system offset calibration takes 2 conversion cycles to complete when chopping is enabled and one

conversion cycle when chopping is disabled. RDY goes high when the calibration is initiated and returns low

when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured

offset coefficient is placed in the offset register of the selected channel.

1

1

1

System Full-Scale Calibration.

User should connect the system full-scale input to the .channel input pins as selected by the CH2-CH0 bits.

A calibration takes 2 conversion cycles to complete when chopping is enabled and one conversion cycle

when chopping is disabled.. RDY goes high when the calibration is initiated and returns low when the

calibration is complete. The ADC is placed in idle mode following a calibration. The measured fullscale

coefficient is placed in the fullscale register of the selected channel.

A fullscale calibration is required each time the gain of a channel is changed.

Table 10. Update Rates Available (Chopping Enabled)

FS3

FS2

FS1

FS0

Tsettle

(ms)

Rejection@ 50 Hz / 60 Hz (Internal Clock)

0

0

0

0

x

x

0

0

0

1

500

5

0

0

1

0

250

8

0

0

1

1

125

16

0

1

0

0

62.5

32

0

1

0

1

50

40

0

1

1

0

41.6

48

0

1

1

1

33.3

60

1

0

0

0

19.6

101

90 dB (60 Hz only)

1

0

0

1

16.6

120

84 dB (50 Hz only)

1

0

1

0

16.6

120

70 dB (50 Hz and 60 Hz)

1

0

1

1

12.5

160

67 dB (50 Hz and 60 Hz)

1

1

0

0

10

200

69 dB (50 Hz and 60 Hz)

1

1

0

1

8.33

240

73 dB (50 Hz and 60 Hz)

1

1

1

0

6.25

320

74 dB (50 Hz and 60 Hz)

1

1

1

1

4.17

480

79 dB (50 Hz and 60 Hz)

With chopping disabled, the update rates remain unchanged but the settling time for each update rate is reduced by a factor of 2. The

rejection at 50 Hz/60 Hz for a 16.6 Hz update rate degrades to 60 dB.

CONFIGURATION REGISTER (RS2, RS1, RS0 = 0, 1, 0; POWER-ON/RESET = 0x0710)

The configuration register is a 16-bit register from which data can be read or to which data can be written. This register is used to configure

the ADC for unipolar or bipolar mode, enable or disable the buffer, enable or disable the burnout currents, select the gain and select the ana-

log input channel. Table 11 outlines the bit designations for the filter register. CON0 through CON15 indicate the bit locations, CON

denoting the bits are in the configuration register. CON15 denotes the first bit of the data stream. The number in brackets indicates the

power-on/reset default status of that bit.

CON15

CON14

CON13

CON12

CON11

CON10

CON9

CON8

VBIAS1(0)

VBIAS0(0)

BO(0)

U/B (0)

0(0)

G2(1)

G1(1)

G0(1)

CON7

CON6

CON5

CON4

CON3

CON2

CON1

CON0

REFSEL1(0)

REFSEL0(0)

REF_DET(0)

BUF(1)

CH3(0)

CH2(0)

CH1(0)

CH0(0)