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LCS7260C Datasheet(PDF) 29 Page - Power Integrations, Inc. |
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LCS7260C Datasheet(HTML) 29 Page - Power Integrations, Inc. |
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29 / 35 page ![]() Rev. D 11/22 29 HiperLCS-2 www.power.com Parameter Symbol Conditions BPS = 12 V T J = 0 °C to 100 °C (Unless Otherwise Specified) Min Typ Max Units Secondary-Side of Safety Isolation Barrier (cont.) D1 and D2 Pin D1, D2 Breakdown Voltage BV D1D2 150 V D1, D2 External Resistor R D1D2(EXT) Recommended external R between SR FET Drain and D1, D2 pin 200 1500 W D1, D2 Inverse Current I D1D2(INV) Allowed current out of D1, D2 when below GND -5 mA D1, D2 SR On Threshold V D1D2ON(TH) See Note E -275 -250 -210 mV D1, D2 SR Off Threshold V D1D2OFF(TH) See Note E 3 8.5 12.5 mV D1, D2 SR Off Threshold Matching ∆ V D1D2OFF -2.6 0 2.6 mV D1, D2 Ouput Bias Current ‒ Off I D1D2OFF Bias Current Out of D1, D2 at V D1D2OFF(TH) -17 -13 -9 m A Secondary Control Over-Temperature Secondary Control Over-Temperature Stop SC (OT)(STOP) See Note A 123 130 137 °C Secondary Control Over-Temperature Start SC (OT)(START) See Note A 75 °C Primary-Side of Safety Isolation Barrier 5VL Pin 5VL Power-Up Threshold V 5VL(UV+) C5VL = 1 mF / 10 V Ceramic 3 3.5 4 V 5VL Power-Up Hysteresis V 5VL(HYST) C5VL = 1 mF / 10 V Ceramic 1.5 V FL Pin FL - Logic 1 Output Voltage V FL(1) I FL = 10 mA, 5VL = 5 V 4.55 4.7 4.929 V FL - Logic 0 Output Voltage V FL(0) I FL = +10 mA 0.17 0.25 0.42 V NOTES: A. Not tested parameter. Guaranteed by design. B. In typical LLC application circuit. C. Normally limited by internal circuitry. D. Not tested parameter. Based on device characterization. E. Production test limits. Observed operational threshold for SR MOSFET drain (D1, D2), also depends on chosen D1, D2 resistors R D1D2(EXT) values. |
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