LCS7260C datasheet(10/35 Pages) POWERINT

10 / 35 page

Rev. D 11/22

HiperLCS-2

www.power.com

PP Pin Selection

Frequency Range

Fault Response

Auto-on

Latch-off

PP External Fault

All

Latch-off

Table 5.

Table of Primary-Side PP Pin Functionality Selections. See Data Table

for PP Pin Selection Resistor Values.

The BM pin is used to signal that the HiperLCS-2 is operating at low

load. Amongst its uses, this signal can be used to turn-on/off an

inrush bypass relay. It could also be used to change the set-point of

the PFC boost voltage.

The FL pin input is used to receive secondary communications, such

as regulation, burst modes and faults. This input receives a digital

0-5 V signal from the FL-output of the isolation device.

HiperLCS-2 Secondary-Side Isolation-Device

Operation

Communications to Primary-Device

As mentioned earlier the primary device will autonomously start-up

and begin switching, with primary remaining in control until the

output voltage reaches close to regulation. At this point the

secondary will take control (primary will hand over control to

secondary) and all further switching is then controlled from the

secondary side controller.

The secondary-device communicates to the primary-device via the

FluxLink isolated communications. Communication commands include

hand over (i.e., secondary taking control), half-bridge switching, burst

mode and declaration of fault condition.

The isolation-device FL-output is connected to the primary FL-input.

Secondary Fault Handling

After hand over the secondary remains in control until either: a

UV-event occurs (primary or secondary), or until a fault occurs

(primary or secondary). Under either of these conditions UV or fault,

the control reverts back to primary control. Also, under either of

these conditions the primary would enter auto-restart. For auto-

restart, the device has two functionalities, either latch (off-condition),

or non-latching (i.e., auto-restart).

After auto-restart off-time, the primary restart is the same as for first

power-up as described earlier in primary control section.

Note that the primary is the device which handles all system level

fault events. Any secondary fault is reported to the primary and

ultimate system level fault response comes from the primary.

Secondary Control

The secondary takes control of switching as the output voltage

approaches regulation. Once in secondary control, the secondary

device uses 3 signals to achieve closed loop control. The FB pin

signal is coupled via resistor divider from the output voltage. This FB

pin voltage represents a scaled version of the output voltage. The FB

pin generates an error signal with respect to an internal 3.75 V DC

reference. The error signal is output via an OTA, operational trans-

conductance (voltage input to current output) amplifier in the form of

an error current signal to the CMP pin. The gain of the OTA amplifier

is dependent on the magnitude of the error signal. Low gain (e.g., 1x.),

is used for small errors, but once error exceeds a threshold the gain is

increased to high gain (e.g. 4x.). This non-linear amplification (NLA)

allows for extremely fast large-signal transient response.

The CMP pin is coupled to an external resistor capacitor compensation

network (two poles one zero). This compensation network is tailored

to achieve good phase-gain response. The error current signal is

integrated and filtered by the compensation network. When the

system is in regulation the error-current-signal should be extremely

small, thus a small current causing very small variations in the CMP

voltage (compensation network). Both leakage and magnetizing

signals.

The IS pin senses the winding voltage from the transformer. The

sense winding is coupled to the primary of the transformer (both

leakage and magnetizing signals), generating a voltage whose

magnitude is similar in scale to that of the main output voltage

winding. The IS pin has internal clamping at 2.5 V. The sense

winding voltage is AC coupled (via capacitor) and then converted to a

current using a resistor into the IS pin. The magnitude of the current

is low, below 35 mA, thus causing minimal system loss.

Internally the IS pin AC-coupled current signal is compared against

the CMP pin voltage. When the two cross this indicates the end of a

half-cycle.

The IS pin signal contains, amongst other things, information about

primary input current. This means that the overall system implements

a current mode control. The control system does not directly control

frequency, but instead controls half-cycle by half-cycle in time-domain.

However, the frequency is an indirect function of the control loop,

thus in steady state the frequency will be stable and a function of

resonant tank, input voltage and output power, etc.

PS Pin

Selection

Burst

Threshold

(%) **

Constant

Current

Compatible

Burst

Control

Internal

Yes

Internal

Yes

Internal

Table 6.

Table of Secondary-Side PS Pin Functionality Selections. Selected via

PS Pin Resistor (see data table). **Approximate Burst Percentage of

Maximum Continuous System Output Power.

Burst Mode

The CMP pin voltage is inversely proportional to primary input

current. This voltage is used to determine when the system should

enter burst mode. Thus, for a given input voltage the burst mode

entry point is a function of output power. This function is compensated

for input voltage, such that the burst-entry point should be at

relatively similar power levels over the entire input voltage range.

For the HiperLCS-2 the burst mode is used for more than one reason.

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