LCS7260C datasheet(11/35 Pages) POWERINT

11 / 35 page

Rev. D 11/22

HiperLCS-2

www.power.com

The first reason for burst is to maintain system efficiency. In full

frequency mode the system efficiency naturally drops significantly

below 10% load. So, the first goal is to enter burst mode before 10%.

The regulation is achieved by switching less often but continuing to

deliver the equivalent of about 10% power per switched half-cycle.

The second goal once in burst is to maintain output regulation.

This is achieved using three modes of burst regulation.

The third goal once in burst is to maintain the switching frequency

envelope well below the audio resonant frequency of the LLC

transformer. The audio/mechanical resonance LLC-transformers is

typically in the 7-12 kHz range. Thus, in burst the HiperLCS-2 intends

to maintain switching frequency envelope below approximately 1 kHz.

Being well below the audio resonance of the transformer means that

there will be little or no noise from the transformer.

The fourth goal is to maintain ability to satisfy 0-100% load step

without losing regulation.

To help achieve the goals above, the HiperLCS-2 uses 3 modes of

operation when in burst.

On entering burst, the highest power burst mode is called

intermediate mode (IM-burst). In this mode the system is still in

closed loop analog control via the CMP pin. The IM-burst works by

forcing off-time at a 1.5 ms repeat period. The IM-mode off-time is

terminated once the output voltage decays to a minimum value

OUTMIN). At this point switching begins again and the analog

control loop closes to reach regulation. Regulation is then maintained

until the off-to-off timer again reaches the 1.5 ms period. Then the

next IM-mode off-time begins.

The next level down in terms of output power, is the light-load

LL-mode burst. During this mode the CMP is no longer used.

Instead, an internal VCMP_BURST is used, where VCMP_BURST

corresponds to the equivalent of 10% load. The LL-mode burst

switching begins when output voltage reaches V

OUTMIN. The

switching continues, terminating when output voltage exceeds

OUTMAX. The device enters LL-off-time until the voltage again

reaches V

OUTMIN. During the LL-burst switching each half-cycle

delivers equal power (determined by internal VCMP_BURST) and

approximately equal to 10% load.

The lowest level of burst in terms of output power is super-light

SL-burst. During this mode the switching occurs after a maximum

off-time of 50 ms. The start SL-burst switching depends on the 50 ms

off-time only. If the output voltage drops as far as V

OUTMIN then the

device will move back to LL-burst. During SL-burst switch, the burst

switches until either it reaches V

OUTMAX or reaches 60 ms of total

switching time.

With the burst modes of the HiperLCS-2 the device is able to achieve

exceptional system no-load performance. Unlike other systems

though it can still accommodate a full 0-100% load step without

dropping out of regulation. The burst mode also intrinsically

manages audio noise. The output ripple during burst is also entirely

bounded by the V

OUTMIN and VOUTMAX of the system. The device

achieves 1% system regulation, internally the FB pin V

OUTMAX and

OUTMIN thresholds are fixed at ±0.65% of VOUTREG.

SR (Synchronous Rectifier) Control

The D1 and D2 pins monitor the drain voltage of the SR MOSFET’s.

When D1 and D2 go below ground this indicates the potential start of

SR conduction. Pins D1 and D2 require a small series resistor to

prevent excessive substrate current when below ground voltage.

Under certain conditions, there may be ringing on D1 and D2, and the

ring may temporarily go below ground only to rise back above

ground. The HiperLCS-2 therefore employs a learning engine to

ignore the ringing. Therefore, when the ring-filtered value of D1

(or D2) goes below a turn-on threshold, the associated SR MOSFET is

then activated. Once activated the D1 (or D2) signals then monitor

the on-state Drain-Source voltage across the SR MOSFET. This gives

an indication of conduction current. For an LLC-converter in

discontinuous conduction mode (DCM), the rectified output current

(i.e., power delivered to the secondary), will reach zero before the

end of the half-cycle. In discontinuous mode (DCM) LLC operation,

the detected D1 (or D2) will terminate the SR-conduction when

current approaches zero. The secondary controller turns off the

SR MOSFET before reverse conduction. For an LLC-converter

operating in continuous conduction mode (CCM), the current will not

reach zero prior to the end of the half-cycle. Therefore, to prevent

reverse SR MOSFET current, the HiperLCS-2 will terminate SR-

conduction prior to half-bridge switching. This can be done because

the half-bridge switching signal is originated at the secondary

controller. Thus, the secondary control can turn off the SR MOSFET

at exactly the latest possible moment to guarantee no shoot-thru in

CCM mode. This is something that allows the HiperLCS-2 to safely

operate in CCM-mode with maximum SR conduction. Note: that in

CCM mode, the primary and secondary rms currents are reduced vs.

DCM mode. Therefore, being able to operate in safely in CCM mode

generally results in higher system efficiency.

SR Driver Voltage Clamp

The G1 and G2 pins respectively drive the SR MOSFET’s for each

phase of the LLC secondary. The BPS pin voltage supplies drive

current to the G1 and G2 gate-drive outputs. However, the BPS pin

is able to accommodate a voltage range of up to 24 V. This would

exceed the maximum gate withstand for most SR MOSFETs. Also,

most SR MOSFET’s are fully enhanced at voltages well below that.

In order to limit the SR-MOSFET gate-charge/discharge energy, the

HiperLCS-2 provides an internal voltage clamp to limit the maximum

voltage output on the G1 and G2 SR-drive pins. The gate-drive

voltage is internally controlled to a maximum of either 11.5 V or 6.5 V.

The maximum voltage depends on the selected frequency range of

the device. Frequency ranges 0,1 (90, 120 kHz), receive 11.5 V

whereas higher frequency ranges 2,3 (180, 240 kHz) receive 6.5 V

drive limits. Limiting the SR MOSFET drive voltage limits the

gate-charge/discharge losses. Typically, higher frequency SR MOSFET’s

are structurally optimized to have lower V

GS turn-on thresholds and

thus fully enhanced at lower voltages.

Layout Connections and Recommended Values

During PC-board layout, it is important to understand the current

return pin for each signal, so that correct routing paths can be

implemented. The following table shows that information along with

generic recommended external component values. Obviously for all

designs component values may change or be optimized to suit

specific conditions, however the recommended values are given as a

good starting point.

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