LCS7260C datasheet(5/35 Pages) POWERINT

5 / 35 page

Rev. D 11/22

HiperLCS-2

www.power.com

HiperLCS-2 Basic Operation

The HiperLCS-2 is designed for half-bridge LLC converters, which are

high-efficiency resonant ZVS, variable frequency converters.

HiperLCS-2 comes as a chipset with two devices: the power-device,

and the isolation device. The power-device (LCS726x) is on the

primary side of the isolation barrier and includes an LLC controller

with built-in high-side and low-drivers and half-bridge power-MOSFETs.

The isolation-device (LSR2000) straddles the isolation barrier to

facilitate communications to the power-device (primary device). The

isolation-device also includes the secondary controller and SR-driver.

The HiperLCS-2 is able to operate with nominal frequencies of up to

240 kHz. It offers extremely high conversion efficiency coupled with

low-component count and rugged protection features.

HiperLCS-2 Primary-Side Power-Device Operation

Start-Up Self-Bias

The HiperLCS-2 provides self-powered start-up. This means that the

system provides a high-voltage bus to the HD pin and the HiperLCS-2

device will take care the rest. Self-powering is accomplished using

internal high-voltage current sources. The first current source is

connected between HD and the BPL pin. When voltage is applied to

HD, the BPL will begin to charge any capacitance connected to this

pin. There is a low pre-charge current which allows initial charging

voltage to be established, and then as BPL voltage increases, this

charge current is stepped to a much higher level allowing faster

start-up times. This higher current capability of the BPL charging also

allows the HiperLCS-2 to provide bias power to a PFC stage and allow

the PFC to begin switching prior to the HiperLCS-2. Once the BPL

self-charge reaches the target voltage it will enter hysteretic control.

The internal current source is disabled during normal operation once

an external bias (from a transformer bias winding), becomes active.

The BPH pin is charged in very similar way to BPL, but the charge

current from HD to BPH is lower. The BPH pin internal charge current

will likewise be disabled once external bias becomes available.

In order to begin switching of an LLC converter ideally, we would

prefer the half-bridge and resonant capacitor voltages to be in a

known condition (preferably close to zero). The HiperLCS-2 achieves

this using a high-voltage current source connected to the HB pin.

This HB current source pre-conditions the resonant tank components

pulling current to ground (return), prior to beginning switching. Doing

this means that at initial start or restart, the HiperLCS-2 always starts

with known tank conditions. The result is that the HiperLCS-2 can

achieve resonant switching on the second switch edge. The

pre-condition HB-current source is active prior to switching while the

high-side device is below UV condition.

After all the charging conditions are complete and all undervoltage

conditions are cleared, HiperLCS-2 begins switching with the

high-side power-MOSFET first.

Start-Up Primary Soft-Start

The HiperLCS-2 begins primary switching at a frequency approximately

1.5x the maximum of the selected switching frequency range. The

switching frequency is ramped down quickly to build current in the

resonant tank. Once the resonant tank achieves target current

HB(IOVL)), the frequency is then indirectly regulated to maintain tank

current at this level. The result at the system output capacitor, is

equivalent to a very high-power current source. This results in a

monotonic rise at the voltage on the output capacitor. The positive

slew rate of the output voltage-rise will be a function of resonant tank

and output capacitor values. There are two selectable thresholds,

HB(OVL) and IHB(IOVL-). The higher level IHB(OVL), is the default value,

selected by using L pin for input voltage UV/OV functions. The lower

level I

HB(IOVL-) is selected by grounding L pin and using PP pin PG

function instead. Selecting I

HB(IOVL-) will slow the output voltage

positive start-up slope and minimizes magnitude of output overshoot.

Selecting I

HB(IOVL-) is recommended for systems using an active PFC

boosted input bus and requires the PFC boost to provide a power-

good (PG) signal to the PP pin. Engagement of arbitrary output loads

will slow the output voltage-rise but will not change the polarity of

the output voltage slope. Primary control of switching continues until

the output voltage reaches close to regulation at which point the

secondary will take control of switching.

Auto Dead Time

The LLC-converter has a structure where positive and return voltages

connect sequentially via power-MOSFET’s to the mid-point or

half-bridge node. The half-bridge connects to a resonant-tank

network which is then series connected to typically power-return

(ground) and coupled to output load. The high-side power-MOSFET

and low-side power-MOSFET are driven sequentially (i.e., neither

MOSFET is on at the same time). During on-time the resonant-tank

delivers some energy to the output and stores the remaining energy.

When the first power-MOSFET turns-off, there is a period of dead

time before the second power-MOSFET turns on. During dead time

some of the remaining stored energy in the resonant tank, continues

to circulate current in the lumped half-bridge capacitance, causing the

half-bridge voltage to slew towards the next switch. The half-bridge

voltage slew continues until either the voltage is clamped by a

MOSFET body-diode (ZVS), or the tank runs out of energy (non-ZVS).

The goal for the LLC-converter is to always run in ZVS (zero-voltage-

switching), operation. This is where the voltage across the next

power-MOSFET is close to zero prior to turning on the power-MOSFET.

This results in near zero capacitive (COSS) MOSFET losses. After the

first power-MOSFET turns-off, the HiperLCS-2 auto-dead time function

holds off second power-MOSFET until the controller detects either the

end of half-bridge voltage-slew or abnormally reaches maximum dead

time. Following this the second power MOSFET will turn-on. The

dead time of a given LLC-converter may vary with input voltage and

output load. The HiperLCS-2 will automatically adjust dead times in

the range from ~90-500 ns.

Frequency

Range

Min

Nom

Max

Unit

135

kHz

120

183

kHz

180

270

kHz

240

366

kHz

Table 2.

Table of Primary and Secondary Frequency Ranges Selections.

Primary Device Frequency Range Selection via PP Pin Resistor

(see data table). Secondary Device Frequency Range Selection

by Part Number.

Primary Protection and Fault Response

If secondary controller does not wake up within 32 ms of primary

switching start, then the power device will declare fault. If hand over

to secondary control does not occur within a further 32 ms after

secondary wake-up, then the primary will declare a fault. As with all

faults, the primary is the master of fault management. When a fault

is declared (primary or secondary), the device will go into either

latching (off) or non-latching fault handling.

For non-latching faults the primary device will initiate auto-restart.

Auto-restart has two responses a short fault response and a long

response (see Table 2).

LCS7260C Datasheet(PDF) 5 Page - Power Integrations, Inc.

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