September 1993

12

Philips Semiconductors

Product specification

4-Bit x 64-word FIFO register; 3-state

74HC/HCT7403

AC WAVEFORMS

Shifting in sequence FIFO empty to FIFO full

Notes to Fig.6

1. DIR initially HIGH; FIFO is prepared for valid data

2. SI set HIGH; data loaded into input stage

3. DIR goes LOW, input stage “busy”

4. SI set LOW; data from first location “ripple through”

5. DIR goes HIGH, status flag indicates FIFO prepared for additional data

6. Repeat process to load 2nd word through to 64th word into FIFO

DIR remains LOW; with attempt to shift into full FIFO, no data transfer occurs.

Fig.6

Waveforms showing the SI input to DIR output propagation delay, the SI pulse width and SI maximum

pulse frequency.

handbook, full pagewidth

MGA659

VM

(1)

1/f max

W

t

t PHL

t PLH

VM

(1)

1st word

2nd word

64th word

7

3

15

6

4

2

SI INPUT

Dn INPUT

DIR OUTPUT