7403 datasheet(28/28 Pages) PHILIPS

28 / 28 page

September 1993

Philips Semiconductors

Product speciﬁcation

4-Bit x 64-word FIFO register; 3-state

74HC/HCT7403

Sequence 2 (FIFOB runs full)

After the MR pulse, a series of 64 SI pulses are applied. When 64 words are shifted in, DIRB remains LOW due to FIFOB

being full (5). DORA goes LOW due to FIFOA being empty.

Sequence 3 (FIFOA runs full)

When 65 words are shifted in, DORA remains HIGH due to valid data remaining at the output of FIFOA. QnA remains

HIGH, being the polarity of the 65th data word (6). After the 128th SI pulse, DIR remains LOW and both FIFOs are full

(7). Additional pulses have no effect.

Sequence 4 (both FIFOs full, starting SHIFT-OUT process)

SIA is held HIGH and two SOB pulses are applied (8). These pulses shift out two words and thus allow two empty

locations to bubble-up to the input stage of FIFOB, and proceed to FIFOA (9). When the first empty location arrives at the

input of FIFOA, a DIRA pulse is generated (10) and a new word is shifted into FIFOA. SIA is made LOW and now the

second empty location reaches the input stage of FIFOA, after which DIRA remains HIGH (11).

Sequence 5 (FIFOA runs empty)

At the start of sequence 5 FIFOA contains 63 valid words due to two words being shifted out and one word being shifted

in, in sequence 4. An additional series of SOB pulses are applied. After 63 SOB pulses, all words from FIFOA are shifted

into FIFOB. DORA remains LOW (12).

Sequence 6 (FIFOB runs empty)

After the next SOB pulse, DIRB remains HIGH due to the input stage of FIFOB being empty. After another 63 SOB pulses,

DORB remains LOW due to both FIFOs being empty (14). Additional SOB pulses have no effect. The last word remains

available at the output Qn.

PACKAGE OUTLINES

See

“74HC/HCT/HCU/HCMOS Logic Package Outlines”.

7403 Datasheet(PDF) 28 Page - NXP Semiconductors