September 1993

16

Philips Semiconductors

Product specification

4-Bit x 64-word FIFO register; 3-state

74HC/HCT7403

With FIFO empty; SO is held HIGH in anticipation

Notes to Fig.10

1. FIFO is initially empty, SO is held HIGH

2. SI pulse; loads data into FIFO and initiates ripple through process

3. DOR flag signals the arrival of valid data at the output stage

4. Output transition; data arrives at output stage after the specified propagation delay between the rising edge of the

5. DOR goes LOW; data shift-out is complete, FIFO is empty again

6. SO set LOW; necessary to complete shift-out process. DOR remains LOW, because FIFO is empty.

Fig.10 Waveforms showing ripple through delay SI input to DOR output, DOR output pulse width and propagation

handbook, full pagewidth

SI INPUT

MGA658

35

Q OUTPUT

n

DOR OUTPUT

VM

(1)

2

ripple through

delay

VM

(1)

6

4

SO INPUT

t PLH

t PLH

t PHL

VM

(1)

1

t W