7403 datasheet(26/28 Pages) PHILIPS

26 / 28 page

September 1993

Philips Semiconductors

Product speciﬁcation

4-Bit x 64-word FIFO register; 3-state

74HC/HCT7403

Notes to Fig.22

1. FIFOA and FIFOB initially full, SIB held HIGH in anticipation of shifting in new data as an empty location bubbles-up

2. Unload one word from FIFOB; SO pulse applied, results in DOR pulse

3. DIRB and SOA pulse HIGH; (bubble-up delay after SOB LOW) data is loaded into FIFOB as a result of the DIR pulse,

data is shifted out of FIFOA

4. DORA and SIB go LOW; flag indicates the output stage of FIFOA is busy, shift-in to FIFOB is complete

5. DORA and SIB go HIGH; flag indicates valid data is again available at FIFOA output stage, SIB is held HIGH, awaiting

bubble-up of empty location

6. DIRA goes HIGH; (bubble-up delay after SOA LOW) an empty location is present at input stage of FIFOA.

Fig.22 FIFO to FIFO communication; output timing under full condition.

handbook, full pagewidth

(1)

DOR B

SO B

(1)

MGA667

DIR A

Q nA

SO A

DIR B

DORA SI B

(1)

bubble - up

delay

(1)

bubble - up

delay

7403 Datasheet(PDF) 26 Page - NXP Semiconductors