September 1993

24

Philips Semiconductors

Product specification

4-Bit x 64-word FIFO register; 3-state

74HC/HCT7403

Expanded format

Figure 20 shows two cascaded FIFOs

providing a capacity of 128 words x

4 bits. Figure 21 shows the signals on

the nodes of both FIFOs after the

application of a SI pulse, when both

FIFOs are initially empty. After a

ripple through delay, data arrives at

pulse width and the timing between

After a second ripple through delay,

Figure 22 shows the signals on the

nodes of both FIFOs after the

FIFOs are initially full. After a

second bubble-up delay an empty

the waveforms at all external nodes of

both FIFOs during a complete shift-in

and shift-out sequence.

Note to Fig.20

The “7403” is easily cascaded to increase word capacity without any external circuitry. In cascaded format, all necessary

communications are handled by the FIFOs. Figures 21 and 22 demonstrate the intercommunication timing between

shifted empty again.

Fig.20 Cascading for increased word capacity; 128 words x 4 bits.

MGA679

DIR

OE

SI

MR

DnA

4

DIR

SI

DOR

SO

DATA INPUT

A

A

4

SO A

DOR A

QnA

7403

FIFO A

DIR

OE

SI

MR

DnB

B

B

4

SOB

DOR B

Q nB

7403

FIFO B

DATA OUTPUT

OE

MR