7403 datasheet(4/28 Pages) PHILIPS

4 / 28 page

September 1993

Philips Semiconductors

Product speciﬁcation

4-Bit x 64-word FIFO register; 3-state

74HC/HCT7403

Fig.4 Functional diagram.

MGA679

DIR

DnA

DIR

DOR

DATA INPUT

SO A

DOR A

QnA

7403

FIFO A

DIR

DnB

SOB

DOR B

Q nB

7403

FIFO B

DATA OUTPUT

FUNCTIONAL DESCRIPTION

A DIR flag indicates the input stage

status, either empty and ready to

receive data (DIR = HIGH) or full and

busy (DIR = LOW). When DIR and SI

are HIGH, data present at D0 to D3 is

shifted into the input stage; once

complete DIR goes LOW. When SI is

set LOW, data is automatically shifted

to the output stage or to the last

empty location. A FIFO which can

receive data is indicated by DIR set

HIGH.

A DOR flag indicates the output stage

status, either data available (DOR =

HIGH) or busy (DOR = LOW). When

SO and DOR are HIGH, data is

available at the outputs (Q0 to Q3).

When SO is set LOW new data may

be shifted into the output stage, once

complete DOR is set HIGH.

Expanded format (see Fig.17)

The DOR and DIR signals are used to

allow the “7403” to be cascaded. Both

parallel and serial expansion is

possible.

Serial expansion is only possible with

typical devices.

Parallel expansion

Parallel expansion is accomplished

by logically ANDing the DOR and DIR

signals to form a composite signal.

Serial expansion

Serial expansion is accomplished by:

• tying the data outputs of the first

device to the data inputs of the

second device

• connecting the DOR pin of the first

device to the SI pin of the second

device

• connecting the SO pin of the first

device to the DIR pin of the second

device.

7403 Datasheet(PDF) 4 Page - NXP Semiconductors

7403 Datasheet(HTML) 4 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL