SW52212 datasheet(52/71 Pages) SILABS

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9.3 Si52204 Pin Descriptions

SS_EN

VDDR

XOUT

VDDX

PWRGD/PWRDNb

REF / SA

XIN/CLKIN

VDD_IO

DIFF_2b

DIFF_2

OE_2b

DIFF_1b

DIFF_1

Si52204

VSSR

VDD

Figure 9.3. 32-pin QFN

Table 9.2. Si52204 32-pin QFN Descriptions

Pin #

Name

Type

Description

SS_EN

Spread spectrum enable pin. 0 = –0.25% spread; mid = Off; 1 = –0.5% spread.

(This pin has an internal 100 kΩ pull-up.)

PWRGD/

PWRDNb

I, PU

Active low input pin asserts power down (PDb) and disables all outputs. (This pin

has an internal 100 kΩ pull-up.) Refer also to settings of Byte 2, Bit2 and Bit3 for

REF. Settings for Bit3 (REF_OE) will take precedence for REF.

XIN/CLKIN

25.00 MHz crystal input or 25 MHz Clock Input.

XOUT

25.00 MHz crystal output. Float XOUT if using only CLKIN (Clock input).

VDDX

PWR

Power supply for crystal

VDDR

PWR

Power supply for REF output

REF /SA

O/I

REF = 25 MHz LVCMOS output. SA = Address select for I2C. When part is pow-

ered up, SA will be latched to select the I2C address. Refer to Table 8.1 SA State

on First Application of PWRGD/PWRDNb on page 32. Refer also to 5.14 REF/SA

Pin for termination. (This pin has an internal 60 kΩ pull-up.)

VSSR

GND

Ground

SDA

I/O

I2C compatible SDATA

SCLK

I2C compatible SCLOCK

Frequency select pin. 0 = 100 MHz; mid = 200 MHz; 1 = 133 MHz. (This pin has an

internal 100 kΩ pull-down.)

DIFF_0

O, DIF

0.7 V, 100 MHz differential clock

DIFF_0b

O, DIF

0.7 V, 100 MHz differential clock

OE_0b

I, PD

Output enable for DIFF_0 pair. (This pin has an internal 100 kΩ pull-down.) 0 = En-

able outputs; 1 = Disable outputs

VDD_IO

PWR

Output power supply

OE_1b

I, PD

Output enable for DIFF_1 pair. (This pin has an internal 100 kΩ pull-down.) 0 = En-

able outputs; 1 = Disable outputs

DIFF_1

O, DIF

0.7 V, 100 MHz differential clock

Data Sheet

Pin Descriptions

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