SW52212 datasheet(29/71 Pages) SILABS

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8. Control Registers

8.1 I2C Interface

To enhance the flexibility and function of the clock synthesizer, an I2C interface is provided. Through the I2C interface, various device

functions, such as individual clock output buffers, are individually enabled or disabled. The registers associated with the I2C interface

initialize to their default setting at power-up. The use of this interface is optional. Clock device register changes are normally made at

system initialization, if any are required.

8.2 Block Read/Write

The clock driver I2C protocol accepts block write and block read operations from the controller. For block write/read operation, access

the bytes in sequential order from lowest to highest (most significant bit first) with the ability to stop after any complete byte is transfer-

red. The block write and block read protocol is outlined in Table 8.2 Block Read and Block Write Protocol on page 32.

8.3 Block Read

After the slave address is sent with the R/W condition bit set, the command byte is sent with the MSB = 0. The slave acknowledges the

register index in the command byte. The master sends a repeat start function. After the slave acknowledges this, the slave sends the

number of bytes it wants to transfer (>0 and <7). The master acknowledges each byte except the last and sends a stop condition.

Slave

A Command Code

Command

starT

Condition

Block Read Protocol

Acknowledge

repeat starT

read

MSB = 0

1 1

Master to

Slave to

Slave

A r

1 1

Data Byte A

Data Byte 0 A Data Byte 1 N P

1 1

Not acknowledge

stoP Condition

Figure 8.1. Block Read Protocol

Data Sheet

Control Registers

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