SW52212 datasheet(54/71 Pages) SILABS

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9.4 Si52202 Pin Descriptions

XOUT

VDDX

PWRGD/PWRDNb

XIN/CLKIN

VDD_IO

DIFF_0b

DIFF_0

OE_0b

GND

Si52202

VSSR

Figure 9.4. 20-pin QFN

Table 9.3. Si52202 20-pin QFN Descriptions1

Pin #

Name

Type

Description

PWRGD/

PWRDNb

I, PU

Active low input pin asserts power down (PDb) and disables all outputs (This pin

has an internal pull-up).

XIN/CLKIN

25.00 MHz crystal input or 25 MHz Clock Input.

XOUT

25.00 MHz crystal output. Float XOUT if using only CLKIN (Clock input).

VDDX

PWR

Power supply for crystal

VSSR

GND

Ground

SDA

I/O

I2C compatible SDATA

SCLK

I2C compatible SCLOCK

SS_EN

Spread spectrum enable pin. 0 = –0.25% spread; mid = Off; 1 = –0.5% spread.

(This pin has an internal 100 kΩ pull-up.)

GND

Ground

VDD

PWR

Power supply

GND

Ground

DIFF_0

O, DIF

0.7 V, 100 MHz differential clock

DIFF_0b

O, DIF

0.7 V, 100 MHz differential clock

OE_0b

I, PD

Output enable for DIFF_0 pair. (This pin has an internal 100 kΩ pull-down.) 0 = En-

able outputs; 1 = Disable outputs

VDD_IO

PWR

Output power supply

OE_1b

I, PD

Output enable for DIFF_1 pair. (This pin has an internal 100 kΩ pull-down.) 0 = En-

able outputs; 1 = Disable outputs

DIFF_1

O, DIF

0.7 V, 100 MHz differential clock

DIFF_1b

O, DIF

0.7 V, 100 MHz differential clock

VDDA

PWR

Analog Power Supply

Data Sheet

Pin Descriptions

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