SW52212 datasheet(16/71 Pages) SILABS

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Parameter

Symbol

Condition

Min

Typ

Max

Unit

OE_b Latency

TOEBLAT

Differential outputs start after

OE_b assertion Differential out-

puts stop after OE_b deassertion

—

3.5

clocks

PWRDNb Latency to differ-

ential outputs enable

TPWRDNb

Differential outputs enable after

PD_b de-assertion

—

490

520

µs

Note:

1. This is for XTAL mode only. For CLKIN mode, there would be a duty cycle distortion spec of ±0.5 ns.

Table 4.4. PCIe and Intel QPI Jitter Specifications

Parameter

Symbol

Condition

Min

Typ

Max

Jitter

Limit

Unit

DIFF HCSL

Cycle to Cycle Jitter

JCCJ

Measured at 0 V differential

—

(pk-pk)

PCIe Gen 1 Pk-Pk Jitter

JPk-Pk

PCIe Gen 1

(pk-pk)

PCIe Gen 2 Phase Jitter

JRMSGEN2

10 kHz < F < 1.5 MHz

0.18

0.24

(RMS)

1.5 MHz < F < Nyquist

1.4

1.7

3.1

(RMS)

PCIe Gen 3 Phase Jitter

JRMSGEN3

Includes PLL BW 2–4 MHz,

CDR = 10 MHz

—

0.3

0.38

1.0

(RMS)

PCIe Gen 3 SRIS1

Phase Jitter

JRMSGen3_SRIS

Includes PLL BW 2–4 MHz,

CDR = 10 MHz

—

0.37

0.44

0.7

(RMS)

PCIe Gen 4 Phase Jitter

JRMSGen4

Includes PLL BW 2–4 MHz,

CDR = 10 MHz

—

0.3

0.38

0.5

(RMS)

PCIe Gen 4 SRIS1

Phase Jitter

JRMSGen4_SRIS

Includes PLL BW 2–4 MHz,

CDR = 10 MHz

—

0.38

0.45

0.5

(RMS)

PCIe Gen 5 5

Phase Jitter

JRMSGen5

Includes PLL BW 500 kHz–1.8 MHz,

CDR = 20 MHz

—

0.11

0.135

0.15

(RMS)

PCIe Gen 5 SRIS1

Phase Jitter

JRMSGen5_SRIS

Includes PLL BW 500 kHz–1.8 MHz,

CDR = 20 MHz

—

0.11

0.13

0.18

(RMS)

Data Sheet

Electrical Specifications

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SW52212 Datasheet(PDF) 16 Page - Silicon Laboratories

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