SW52212 datasheet(22/71 Pages) SILABS

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5.4 Power Supply Filtering Recommendations

VDDR

VDD_IO

VDD

VDDA

VDDX

Si52202/04/08/12

0.1uF

1uF

FB1

FB2

FB3

FB5

Placed near

the part

VDD_CORE

( 1.5V or 1.8V)

VDD_IO

(1V to VDD_CORE)

Recommended ferrite bead specs:

600 Ω at 100 MHz, ≤ 0.1 Ω DCR max., ≥40mA current rating

For parts that have

multiple VDD pins, use

one 0.1uF capacitor

per pin.

For parts that have

multiple VDD_IO pins,

use one 0.1uF

capacitor per pin.

0.1uF

1uF

VDD_IO

FB4

Figure 5.3. Power Supply Filtering

Separate out each type of VDD (VDD, VDDA, VDDX, VDDR, and VDD_IO) using ferrite beads. Then, for each VDD type use one 1 µF

bulk capacitor along with an additional 0.1 µF capacitor for each individual VDD pin. All VDD Core (VDD, VDDA, VDDX, and VDDR)

pins should be tied to the same voltage, either 1.8 V or 1.5 V. The VDD_IO pins can be tied to a voltage between 1 V and the selected

VDD Core voltage. Note, the VDD_IO pins must all be tied to the same voltage.

5.5 PWRGD/PWRDNb (Power Down) Pin

The PWRGD/PWRDNb pin is a dual-function pin. During initial power up, the pin functions as the PWRGD pin. Upon the first power up,

if the PWRGD pin is low, all outputs, the crystal oscillator, and the I2C logics will be disabled. Once the PWRGD pin has been sampled

high by the clock chip, the pin assumes a PWRDNb functionality. When the pin has assumed a PWRDNb functionality and is pulled

low, the device will be placed in power down mode. The assertion and dessertion of PWRDNb is asynchronous. This pin has a 100 kΩ

internal pull-up.

Figure 5.4. Initial Sample High of PWRGD/PWRDNb After Power Up

Data Sheet

Functional Description

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