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SAF784X Datasheet(PDF) 32 Page - NXP Semiconductors

Part # SAF784X
Description  One chip CD audio device with integrated MP3/WMA decoder
PDF  93 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

SAF784X Datasheet(HTML) 32 Page - NXP Semiconductors

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SAF784X_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2008
32 of 93
NXP Semiconductors
SAF784x
One chip CD audio device with integrated MP3/WMA decoder
6.5.5.5
Available signals for monitoring
The operation of the bit detector can be monitored by the microcontroller via an external
pin. Five signals are available for measurement:
PLL frequency signal: The microcontroller monitors this signal by reading register
PLLIntegrator.
Asymmetry signal: This signal is in 2’s complement form and can be read from register
SlicerAssym.
Jitter signal: A jitter measurement is done internally. The zero-crossing jitter value is
available in register PLLJitter.
Internal lock flags.
Jitter signal:
Jitter measurement is done in two steps:
1. The distance between the EFM zero transition and the bit clock zero transition is
measured.
2. The calculated jitter for the zero transition is averaged using a 10-bit low-pass filter.
The top 8-bits of the filter output can be read back from register PLLJitter. To obtain
the jitter in % of the channel bit clock, Equation 3 applies:
(3)
This jitter measurement is also available via the Meas1 telemetry signal on pin CL1. The
full 10-bit output of the filter is available via this pin; see Section 6.5.5.8.
It is also possible to read out an average jitter value via register PLLAverageJitter. This
value is an average of the normal jitter value over a period of 8000 bit clock periods. The
formula to transform this into a percentage is shown in Equation 4:
(4)
6.5.5.6
Use of jitter measurement
The jitter measurement is an absolute-reference jitter measurement. It gives the average
square value of the bit detection jitter. Note that bit-to-clock jitter is measured. In this
device, the bit-to-clock jitter is measured directly before the bit detection, and contains
contributions due to various imperfections of the complete signal path:
• Disc
Table 6.
Jitter input calculation
Distance (
× f
bit)
Average distance (bit clocks)
Jitter filter input (5-bit decimal
integer)
< 2
⁄
16
1
⁄
16
1
2
⁄
16 to
4
⁄
16
3
⁄
16
9
4
⁄
16 to
6
⁄
16
5
⁄
16
25
> 6
⁄
16
7
⁄
16
49
jitter
jitter 7:0
[] 2.83
–
1024
--------------------------------------------
100 %
()
×
=
average jitter
averagejitter 7:0
[] 2.83
–
1024
-----------------------------------------------------------------
100
×
%
()
=



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