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SAF784X Datasheet(PDF) 11 Page - NXP Semiconductors |
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SAF784X Datasheet(HTML) 11 Page - NXP Semiconductors |
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11 / 93 page ![]() SAF784X_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 9 May 2008 11 of 93 NXP Semiconductors SAF784x One chip CD audio device with integrated MP3/WMA decoder 6.1.2 HF acquisition The HF data (EFM) signal is obtained by summing the signals from the three or four central diodes of the OPU and filtering and converting the signals to a digital representation via a 6-bit HF ADC. Figure 4 shows a simplified block diagram of the HF path. The four diode signals D1, D2, D3 and D4 are summed in the first RF amplifier. The gain of the first amplifier is controlled by register AGCGain[7:4]. A second gain stage has been added to lessen the gain bandwidth requirements of a single gain stage operational amplifier and also to act as dynamic Automatic Gain Control (AGC). The gain of this amplifier is set by register AGCGain[3:0] and can be changed on-the-fly from the ARM microprocessor. The gain range accommodates 12 dB of gain needed to boost the signal when the laser tracks across a fingerprint defect on the disc. CD-R, CD-RW, and finger prints, not only reduce the AC signal amplitude compared to a perfectly pressed disc but also reduces the DC pedestal voltage. The high-pass filter will remove all DC present at the input, but offsets will be added by the second and third gain stages. A 5-bit plus-sign DAC controlled by register OffsetComp[5:0] adds a current to compensate for this offset. The current reduces in linear dB steps and follows the AC gain. Fig 4. HF acquisition block diagram 001aag308 20 k Ω RF AMP1 0 dB ... 24 dB register AGCGain[7:4] register RFControl2[1] HIGH-PASS FILTER D1 20 k Ω D2 20 k Ω D3 20 k Ω 20 k Ω 20 k Ω 20 k Ω 80 k Ω 80 k Ω register RFControl2[2] single-ended-to- differential 4 × converter register OffsetComp[5:0] decoded to [31:0] D4 HF_MON RF AMP2 0 dB ... 12 dB register AGCGain[3:0] A NOISE FILTER D E G H H G E D C B A B C noise_filt_sel register RFControl2[3] register RFControl1[6:4] register RFControl1[3:0] 67.7376 MHz from PLL 67.7376 MHz sys_clk register RFControl2[4] register RFControl2[0] register RFControl2[1] register RFControl2[5] rf_adc_out[5:0] to channel decoder |
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