SAF784X datasheet(49/93 Pages) NXP

49 / 93 page

SAF784X_2

Product data sheet

Rev. 02 — 9 May 2008

49 of 93

NXP Semiconductors

SAF784x

One chip CD audio device with integrated MP3/WMA decoder

Tacho trip frequency: It is possible for the software to be notiﬁed with an interrupt when

reaching a speciﬁc speed during spin-up or spin-down. This is done by programming the

desired frequency trip point in register TACHO2. When the tacho frequency goes above or

below this trip point, an interrupt gets generated (bit 3 of register InterruptStatus2). Bit 1

(TACHOINTERRUPTSELECT) of register TACHO3 can be set to enable an interrupt to be

generated when the frequency goes above or below the trip point.

6.6 Parallel Digital Servo IC (PDSIC)

The digital servo block design on the SAF784x has evolved from the design used on the

SAA7824 IC, and is referred to as the PDSIC. ‘Parallel’, refers to the microprocessor

interface of the servo block which is now a high speed parallel interface. Previously, it was

a serial interface used on the SAA7824, 3 or 4-wire, I2C-bus. The PDSIC features are

listed below:

• Programmable ADC for CD-RW playback compatibility

• Diode signal processing

• Signal conditioning

• Focus and radial control system

• Access control

• Sledge control

• Shock detector

• Defect detector

• Off-track counting and detection

• Automatic closed-loop gain control available for focus and radial loops

• Hi-level features

• Flexible servo

6.6.1 PDSIC registers and servo RAM control

The servo block is controlled by two parts of the design: the servo control registers which

are used to control the writing of commands and parameters to the servo, and the servo

RAM. The servo RAM has two roles: storage of the servo parameters, and capture of

commands and parameters during the command process.

All of the servo write commands consist of a command byte followed by a number of

parameter bytes (between one and seven), all of which have to be loaded into the PDSIC

using a serial communication interface.

The command byte is the ﬁrst to be loaded and can be considered as two nibbles. The

upper (most signiﬁcant) nibble represents the command itself whilst the lower (least

signiﬁcant) nibble tells the PDSIC how many parameter bytes to expect. The command

byte gets placed into memory location 0x31 (called oldcom).

Subsequently, parameter bytes get loaded sequentially and these get placed into a stack

space that has been reserved within the memory (locations 0x30 down to 0x2B). With

each parameter byte that is loaded, the value in oldcom is decremented so that the byte

count decreases to zero, and the PDSIC knows it has a complete servo command (a

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