Data Sheet

LT4322

analog.com

Rev. 0

17 of 29

For applications utilizing a 10nF CG capacitor, locate CG as close as possible to the power MOSFET. Place output bulk

capacitors close to the drains and sources of the power MOSFETs. Use a large power plane to minimize the parasitic

inductance in the CATHODE-to-ANODE circuit pathways of the LT4322s.

For the DFN package, pin spacing may be a concern at voltages greater than 30V. Check the creepage and clearance

guidelines to determine if this is an issue. To increase the effective pin spacing between high voltage and ground

pins, leave the exposed pad connection open. Use no-clean flux to minimize PCB contamination.

Figure 25. Recommended PCB Layout

Reverse Recovery

The LT4322 responds very quickly to reverse bias conditions, minimizing reverse current and reverse charge. The

waveforms in Figure 26 illustrate the reverse recovery time. Initially, the LT4322 is driving the gate of the external

power MOSFET to 12V. The current waveform indicates that 3A is flowing in the forward direction from ANODE to

CATHODE. A controlled change in current is used to force reverse current through the power MOSFET at a rate of

100A/µs. In this example, the LT4322 MOSFET gate is fully turned off 50ns after the reverse current is detected,

resulting in a peak reverse current of -3A. The LT4322 turns off even large MOSFETs within 300ns of a sudden reverse

bias condition.

Figure 26. Reverse Recovery Waveforms

ANODE

CONNECTION

CATHODE

CONNECTION

CVDDA

U1

M1

M2

GATE (5V/DIV)

ANODE (5V/DIV)

LOAD (5V/DIV)

CURRENT (1A/DIV)

50ns/DIV

30V

15V

0V

3A

0A

– A