AD9259 datasheet(3/52 Pages) AD

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AD9259

Rev. 0 | Page 3 of 52

SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 1.

AD9259-50

Parameter1

Temperature

Min

Typ

Max

Unit

RESOLUTION

Bits

ACCURACY

No Missing Codes

Full

Guaranteed

Offset Error

Full

±1

±8

Offset Matching

Full

±2

±8

Gain Error

Full

±0.5

±2

% FS

Gain Matching

Full

±0.3

±0.7

% FS

Differential Nonlinearity (DNL)

Full

±0.5

±1.0

LSB

Integral Nonlinearity (INL)

Full

±1.5

±3.5

LSB

TEMPERATURE DRIFT

Offset Error

Full

±2

ppm/°C

Gain Error

Full

±17

ppm/°C

Reference Voltage (1 V Mode)

Full

±21

ppm/°C

REFERENCE

Output Voltage Error (VREF = 1 V)

Full

±5

±30

Load Regulation @ 1.0 mA (VREF = 1 V)

Full

Input Resistance

Full

kΩ

ANALOG INPUTS

Differential Input Voltage Range (VREF = 1 V)

Full

V p-p

Common-Mode Voltage

Full

AVDD/2

Differential Input Capacitance

Full

Analog Bandwidth, Full Power

Full

315

MHz

POWER SUPPLY

AVDD

Full

1.7

1.8

1.9

DRVDD

Full

1.7

1.8

1.9

IAVDD

Full

185

192.5

IDRVDD

Full

32.5

34.7

Total Power Dissipation (Including Output Drivers)

Full

392

409

Power-Down Dissipation

Full

Standby Dissipation2

Full

CROSSTALK

Full

−100

CROSSTALK (Overrange Condition)3

Full

−100

1 See the AN-835 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed.

2 Can be controlled via SPI.

3 Overrange condition is specific with 6 dB of the full-scale input range.

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