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AD9259 Datasheet(PDF) 29 Page - Analog Devices |
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AD9259 Datasheet(HTML) 29 Page - Analog Devices |
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29 / 52 page ![]() AD9259 Rev. 0 | Page 29 of 52 DON’T CARE DON’T CARE DON’T CARE DON’T CARE SDIO SCLK CSB tS tDH tHI tCLK tLO tDS tH R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 Figure 59. Serial Timing Details Table 14. Serial Timing Definitions Parameter Timing (minimum, ns) Description tDS 5 Setup time between the data and the rising edge of SCLK tDH 2 Hold time between the data and the rising edge of SCLK tCLK 40 Period of the clock tS 5 Setup time between CSB and SCLK tH 2 Hold time between CSB and SCLK tHI 16 Minimum period that SCLK should be in a logic high state tLO 16 Minimum period that SCLK should be in a logic low state |
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