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SLG51001 Datasheet(PDF) 3 Page - Renesas Technology Corp |
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SLG51001 Datasheet(HTML) 3 Page - Renesas Technology Corp |
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3 / 25 page ![]() SLG51001 PMIC with High PSRR, Low Noise, Multi-Output LDOs and Integrated Load Switch Datasheet Revision 3.01 10-May-2022 CFR0011-120-00 3 of 25 © 2022 Renesas Electronics Corporation 1 Block Diagram SLG51001 Sup plies LDO 1 VOUT 2.4 V to 3.3 V IOUT_MAX 475 mA LDO6 VOUT 0.5 V to 1.2 V IOUT_MAX 1 A or Loa d Switch VIN 0.5 V to 1.25 V RON 40 mΩ Reference IO and Sup ply Controller CS OTP 2. 2 µF VO UT1 VDD Digital Con tro l LDO_CORE GPIO1 to 2 10 µF VOUT6 VIN6 GPIO3_SDA GPI4_SCL LDO 2 VOUT 1.2 V to 3.75 V OUT_MAX 500 mA 0. 45 µF VOUT2 LDO5 VOUT 1.2 V to 3.75 V IOUT_MAX 500 mA 0. 45 µF VO UT5 LDO3 VOUT 1.2 V to 3.75 V IOUT_MAX 500 mA 0. 45 µF VOUT3 VI N3_4 2 LDO4 VOUT 1.2 V to 3.75 V IOUT_MAX 500 mA 0. 45 µF VOUT4 VI N2_5 Figure 1: Block Diagram |
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