SLG51001

PMIC with High PSRR, Low Noise, Multi-Output LDOs

and Integrated Load Switch

Datasheet

Revision 3.01

10-May-2022

CFR0011-120-00

6 of 25

© 2022 Renesas Electronics Corporation

When de-asserting the CS pin, it can have a programmable shutdown debounce time (from 0 µs to

256 µs, register CS_T_DEB).

2.1.2

SCL

– I2C Clock

The SCL signal is the I2C clock.

2.2

Bidirectional Pins

2.2.1

GPIO1 to GPIO3 and GPI4

– General Purpose Input/Output

The general-purpose input/output pins are configurable by dedicated registers (IO_GPIO<x>_CONF).

GPIO1 to GPIO3 can be configured as an input or an open-drain output. GPI4 is always an input pin.

In the LOW IQ RESET state, all GPIOs are configured as inputs with no pull-down.

The user-configurable input levels are 1.2 V and 1.8 V.

2.2.2

SDA

– I2C Data

The SDA signal is the I2C data signal. It is an open-drain signal so that either side can pull it down to

a logic low level.