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SLG51001 Datasheet(PDF) 7 Page - Renesas Technology Corp

Part # SLG51001
Description  PMIC with High PSRR, Low Noise, Multi-Output LDOs and Integrated Load Switch
PDF  25 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SLG51001 Datasheet(HTML) 7 Page - Renesas Technology Corp

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SLG51001
PMIC with High PSRR, Low Noise, Multi-Output LDOs
and Integrated Load Switch
Datasheet
Revision 3.01
10-May-2022
CFR0011-120-00
7 of 25
© 2022 Renesas Electronics Corporation
3
Characteristics
3.1
Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to
the device. These are stress ratings only, so functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of the specification are not implied.
Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Table 3: Absolute Maximum Ratings
Parameter
Description
Conditions
Min
Max
Unit
TSTG
Storage temperature
Non operational
-40
+150
°C
TJ
Junction temperature
-25
+125
°C
TA
Ambient temperature
-40
+85
°C
VDD
Power supply voltage on VDD
pin
-0.3
+6.0
V
Power supply voltage on VIN2_5,
VIN3_4 pins
-0.3
+6.0
V
Power supply voltage on VIN5_6
pin
-0.3
+1.8
V
VPIN_LV
Voltage on low-voltage pins
GPIO1 to GPIO3 and
GPI4
-0.3
+1.98
V
VPIN_HV
Voltage on high-voltage pins
CS
-0.3
VDD +
0.3
V
ESD
ESD Protection (Human Body
Model)
2000
V
ESD Protection (Charged Device
Model)
500
V
3.1.1
Guidelines for Reliable Operation
● Low Voltage Pins: take care that the low voltage pins (GPIO1 to GPIO3, GPI4, and VIN6) do not
exceed their Abs. Max. ratings, even briefly. Transients both positive (above max) and negative
(below min) can cause EOS (Electrical Overstress) damage.
● Power sequencing: CS should not be asserted high before VDD is powered up. CS pin should be
de-asserted before VDD falls out of operating range. VIN supplies for LDO_HV and LDO_LV
channels (VIN2_5, VIN3_4, VIN6) can be safely biased even if VDD is not present. VIN supplies
should be powered up before enabling their respective LDO channels. GPIO’s configured as
inputs are allowed to be forced high before VDD is powered up.
3.2
Recommended Operating Conditions
Table 4: Recommended Operating Conditions
Parameter
Description
Conditions
Min
Typ
Max
Unit
TA
Ambient temperature
-40
+85
°C
VDD
Power supply voltage on
VDD pin
2.8
5.0
V
Power supply voltage on
VIN2_5, VIN3_4 pins
1.7
5.0
V
Power supply voltage on
VIN6 pin
LDO Mode
0.8
1.5
V



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