TMUX8212 datasheet(29/42 Pages) TI

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12 Layout

12.1 Layout Guidelines

The image below illustrates an example of a PCB layout with the TMUX821x device. Some key considerations

are:

• For reliable operation, connect at least one decoupling capacitor ranging from 0.1 µF to 10 µF between VDD

and VSS to GND. We recommend a 0.1 µF and 1 µF capacitor, placing the lowest value capacitor as close to

the pin as possible. Make sure that the capacitor voltage rating is sufficient for the supply voltage.

• Keep the input lines as short as possible.

• Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.

• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if

possible, and only make perpendicular crossings when necessary.

12.2 Layout Example

SEL1

VSS

SEL2

TMUX821x

VDD

N.C.

SEL3

GND

SEL4

Wide (low inductance)

trace for power

Wide (low inductance)

trace for power

Via to ground plane

Figure 12-1. TMUX821x TSSOP Layout Example

VSS

SEL2

SEL1

SEL3

GND

N.C.

SEL4

VDD

Wide (low inductance)

trace for power

Wide (low inductance)

trace for power

Via to ground plane

Figure 12-2. TMUX821x QFN Layout Example

www.ti.com

TMUX8211, TMUX8212, TMUX8213

SCDS434B – OCTOBER 2021 – REVISED MARCH 2023

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