S29PL-J55BAI011 datasheet(75/96 Pages) SPANSION

75 / 96 page

September 22, 2006 S29PL-J_00_A9

S29PL-J

Da ta

Sh e e t

(Adv a n ce

In f o r m ation)

Figure 20.2 Input Waveforms and Measurement Levels

20.3

VCC Ramp Rate

All DC characteristics are specified for a VCC ramp rate > 1V/100 µs and VCC ≥ VCCQ - 100 mV. If the VCC

ramp rate is < 1V/100 µs, a hardware reset required.+

20.4

Read Operations

Notes

1. Not 100% tested.

2. See Figure 20.1 on page 72 and Table 20.1 on page 72 for test specifications

3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC /2. The time from OE# high to the data bus

driven to VCC /2 is taken as tDF.

4. S29PL129J has two CE# (CE1#, CE2#).

5. Valid CE1# / CE2# conditions: (CE1# = VIL,CE2# = VIH) or (CE1# = VIH,CE2# = VIL) or (CE1# = VIH, CE2# = VIH)

6. Valid CE1# / CE2# transitions: (CE1# = VIL,CE2# = VIH) or (CE1# = VIH,CE2# = VIL) to (CE1# = CE2# = VIH)

7. Valid CE1# / CE2# transitions: (CE1# = CE2# = VIH) to (CE1# = VIL,CE2# = VIH) or (CE1# = VIH,CE2# = VIL)

8. For 70 pF Output Load Capacitance, 2 ns will be added to the above tACC,tCE,tPACC,tOE values for all speed grades

VIO

0.0 V

VIO/2

Output

Measurement Level

Input

Table 20.3 Read-Only Operations

Parameter

Description (Notes)

Test Setup

Speed Options

Unit

JEDEC

Std.

tAVAV

tRC

Read Cycle Time (1)

Min

606570

tAVQV

tACC

Address to Output Delay

CE#, OE# = VIL

Max

606570

tELQV

tCE

Chip Enable to Output Delay

OE# = VIL

Max

606570

tPACC

Page Access Time

Max

tGLQV

tOE

Output Enable to Output Delay

Max

tEHQZ

tDF

Chip Enable to Output High Z (3)

Max

tGHQZ

tDF

Output Enable to Output High Z (1, 3)

Max

tAXQX

tOH

Output Hold Time From Addresses,

CE# or OE#, Whichever Occurs First (3)

Min

tOEH

Output Enable Hold Time (1)

Read

Min

Toggle and Data# Polling

Min

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