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S29PL-J55BAI011 Datasheet(PDF) 77 Page - SPANSION |
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S29PL-J55BAI011 Datasheet(HTML) 77 Page - SPANSION |
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77 / 96 page  September 22, 2006 S29PL-J_00_A9 S29PL-J 75 Da ta Sh e e t (Adv a n ce In f o r m ation) 20.5 Reset Note Not 100% tested. Figure 20.5 Reset Timings Notes 1. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH 2. S29PL129J - There are two CE# (CE1#, CE2#). In the below waveform CE# = CE1# or CE2# Table 20.4 Hardware Reset (RESET#) Parameter Description All Speed Options Unit JEDEC Std tReady RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) Max 20 µs tReady RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH Reset High Time Before Read (See Note) Min 50 ns tRPD RESET# Low to Standby Mode Min 20 µs tRB RY/BY# Recovery Time Min 0 ns RESET# RY/BY# RY/BY# tRP tReady Reset Timings NOT during Embedded Algorithms tReady CE#, OE# tRH CE#, OE# Reset Timings during Embedded Algorithms RESET# tRP tRB |
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