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S29PL-J55BAI011 Datasheet(PDF) 78 Page - SPANSION |
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S29PL-J55BAI011 Datasheet(HTML) 78 Page - SPANSION |
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78 / 96 page ![]() 76 S29PL-J S29PL-J_00_A9 September 22, 2006 Data Sheet (Adv an ce Inf o r m a t io n) 20.6 Erase/Program Operations Notes: 1. Not 100% tested. 2. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH 3. S29PL129J - There are two CE# (CE1#, CE2#). 4. See Table 21.4 on page 84 for more information. Table 20.5 Erase and Program Operations Parameter Description Speed Options (ns) JEDEC Std 55 60 65 70 Unit tAVAV tWC Write Cycle Time (Note 1) Min 55606570 tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tWLAX tAH Address Hold Time Min 30 35 ns tAHT Address Hold Time From CE# (CE1#, CE#2 in PL129J) or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 25 30 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 10 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# (CE1# or CE#2 in PL129J) Setup Time Min 0 ns tWHEH tCH CE# (CE1# or CE#2 in PL129J) Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 ns tWHDL tWPH Write Pulse Width High Min 20 25 ns tSR/W Latency Between Read and Write Operations Min 0 ns tWHWH 1 tWHW H1 Programming Operation (Note 4) Typ 6 µs tWHWH 1 tWHW H1 Accelerated Programming Operation (Note 4) Typ 4 µs tWHWH 2 tWHW H2 Sector Erase Operation (Note 4) Typ 0.5 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Write Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Max 90 ns Min 35 ns tPSL Program Suspend Latency Max 35 µs tESL Erase Suspend Latency Max 35 µs |
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