S29PL-J55BAI011 datasheet(24/96 Pages) SPANSION

24 / 96 page

S29PL-J

S29PL-J_00_A9 September 22, 2006

Data

Sheet

(Adv an ce

Inf o r m a t io n)

10.3

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing

sectors of memory), the system must drive WE# and CE# (CE1# or CE#2 in PL129J) to VIL, and OE# to VIH.

The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the

Unlock Bypass mode, only two write cycles are required to program a word, instead of four. Word Program

Command Sequence on page 57 has details on programming data to the device using both standard and

Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device. Table 10.4 on page 21

indicates the set of address space that each sector occupies. A “bank address” is the set of address bits

required to uniquely select a bank. Similarly, a “sector address” refers to the address bits required to uniquely

select a sector. Command Definitions on page 55 has details on erasing a sector or the entire chip, or

suspending/resuming the erase operation.

ICC2 in the DC Characteristics table represents the active current specification for the write mode. See the

timing specification tables and timing diagrams in section Reset on page 75 for write operations.

10.3.1

Accelerated Program Operation

The device offers accelerated program operations through the ACC function. This function is primarily

intended to allow faster manufacturing throughput at the factory.

If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the

time required for program operations. The system would use a two-cycle program command sequence as

required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to normal

operation. Note that VHH must not be asserted on WP#/ACC for operations other than accelerated

programming, or device damage may result. In addition, the WP#/ACC pin should be raised to VCC when not

in use. That is, the WP#/ACC pin should not be left floating or unconnected; inconsistent behavior of the

device may result.

10.3.2

Autoselect Functions

If the system writes the autoselect command sequence, the device enters the autoselect mode. The system

can then read autoselect codes from the internal register (which is separate from the memory array) on

DQ15–DQ0. Standard read cycle timings apply in this mode. Refer to the Table 10.9, Secured Silicon Sector

Addresses on page 39 and Autoselect Command Sequence on page 56 for more information.

10.4

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this

mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state,

independent of the OE# input.

The device enters the CMOS standby mode when the CE# (CE1#,CE#2 in PL129J) and RESET# pins are

both held at VIO ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# (CE1#,CE#2 in

PL129J) and RESET# are held at VIH, but not within VIO ± 0.3 V, the device will be in the standby mode, but

the standby current will be greater. The device requires standard access time (tCE) for read access when the

device is in either of these standby modes, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws active current until the operation

is completed.

ICC3 in DC Characteristics on page 71 represents the CMOS standby current specification.

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