S29PL-J55BAI011 datasheet(22/96 Pages) SPANSION

22 / 96 page

S29PL-J

S29PL-J_00_A9 September 22, 2006

Data

Sheet

(Adv an ce

Inf o r m a t io n)

10. Device Bus Operations

This section describes the requirements and use of the device bus operations, which are initiated through the

internal command register. The command register itself does not occupy any addressable memory location.

The register is a latch used to store the commands, along with the address and data information needed to

execute the command. The contents of the register serve as inputs to the internal state machine. The state

machine outputs dictate the function of the device. Table 10.1 lists the device bus operations, the inputs and

control levels they require, and the resulting output. The following subsections describe each of these

operations in further detail.

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 8.5–9.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In, DIN

= Data In, DOUT = Data Out

Notes

1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See High Voltage Sector

Protection on page 48.

2. WP#/ACC must be high when writing to upper two and lower two sectors.

10.1

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the OE# and appropriate CE# pins (For PL129J -

CE1#/CE2# pins) to VIL. In PL129J, CE1# and CE2# are the power control and select the lower (CE1#) or

upper (CE2#) halves of the device. CE# is the power control. OE# is the output control and gates array data

to the output pins. WE# should remain at VIH.

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory content occurs during the power transition. No command is

necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses

on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for

read access until the command register contents are altered.

Refer to Table 21.3 on page 84 for timing specifications and to Figure 20.3 on page 74 for the timing

diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array

data.

Table 10.1 PL127J Device Bus Operations

Operation

CE#

OE#

WE#

RESET#

WP#/ACC

Addresses

(Amax–A0)

DQ15–

DQ0

Read

AIN

DOUT

Write

X (Note 2)

AIN

DIN

Standby

VIO±0.3 V

VIO ±0.3 V

X (Note 2)

High-Z

Output Disable

High-Z

Reset

High-Z

Temporary Sector Unprotect

(High Voltage)

VID

XAIN

DIN

Table 10.2 PL129J Device Bus Operations

Operation

CE1#

CE2#

OE#

WE#

RESET#

WP#/ACC

Addresses

(A21–A0)

DQ15–

DQ0

Read

AIN

DOUT

Write

(Note 2)

AIN

DIN

Standby

VIO±

0.3 V

VIO ±

0.3 V

VIO ±

0.3 V

High-Z

Output Disable

High-Z

Reset

High-Z

Temporary Sector Unprotect

(High Voltage)

VID

XAIN

DIN

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