S29PL-J55BAI011 datasheet(23/96 Pages) SPANSION

23 / 96 page

September 22, 2006 S29PL-J_00_A9

S29PL-J

Da ta

Sh e e t

(Adv a n ce

In f o r m ation)

10.1.1

Random Read (Non-Page Read)

Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable

access time (tCE) is the delay from the stable addresses and stable CE# to valid data at the output inputs. The

output enable access time is the delay from the falling edge of the OE# to valid data at the output inputs

(assuming the addresses have been stable for at least tACC–tOE time).

10.1.2

Page Mode Read

The device is capable of fast page mode read and is compatible with the page mode Mask ROM read

operation. This mode provides faster read access speed for random locations within a page. Address bits

Amax–A3 select an 8 word page, and address bits A2–A0 select a specific word within that page. This is an

asynchronous operation with the microprocessor supplying the specific word location.

The random or initial page access is tACC or tCE and subsequent page read accesses (as long as the

locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# (CE1# and

CE#2 in PL129J) is deasserted (=VIH), the reassertion of CE# (CE1# or CE#2 in PL129J) for subsequent

access has access time of tACC or tCE. Here again, CE# (CE1# /CE#2 in PL129J)selects the device and OE#

is the output control and should be used to gate data to the output inputs if the device is selected. Fast page

mode accesses are obtained by keeping Amax–A3 constant and changing A2–A0 to select the specific word

within that page.

10.2

Simultaneous Read/Write Operation

In addition to the conventional features (read, program, erase-suspend read, erase-suspend program, and

program-suspend read), the device is capable of reading data from one bank of memory while a program or

erase operation is in progress in another bank of memory (simultaneous operation). The bank can be

selected by bank addresses (PL127J: A22–A20, PL129J and PL064J: A21–A19, PL032J: A20–A18) with

zero latency.

The simultaneous operation can execute multi-function mode in the same bank.

Table 10.3 Page Select

Word

Word 0

Word 1

Word 2

Word 3

Word 4

Word 5

Word 6

Word 7

Table 10.4 Bank Select

Bank

PL127J: A22–A20, PL064J: A21–A19, PL032J: A20–A18

Bank A

000

Bank B

001, 010, 011

Bank C

100, 101, 110

Bank D

111

Bank

CE1#

CE2#

PL129J: A21–A20

Bank 1A

Bank 1B

01, 10, 11

Bank 2A

00, 01, 10

Bank 2B

S29PL-J55BAI011 Datasheet(PDF) 23 Page - SPANSION

S29PL-J55BAI011 Datasheet(HTML) 23 Page - SPANSION

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

Datasheet Download

Link URL