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SC7283 Datasheet(PDF) 41 Page - Sitronix Technology Co., Ltd. |
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SC7283 Datasheet(HTML) 41 Page - Sitronix Technology Co., Ltd. |
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41 / 89 page ![]() SC7283 Version 1.0 Page 41 of 89 2018/11 7.2.3 System Configuration The system configuration is illustrated above and some word-definitions are explained below: a. Transmitter: the device which sends the data to the bus. b. Receiver: the device which receives the data from the bus. c. Master: the device which initiates a transfer generates clock signals and terminates a transfer. d. Slave: the device which is addressed by a master. e. Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message. f. Arbitration: the procedure to ensure that, if more than one master tries to control the bus simultaneously, only one is allowed to do so and the message is not corrupted. g. Synchronization: procedure to synchronize the clock signals of two or more devices. 7.2.4 Acknowledgment Each byte of eight bits is followed by an acknowledge-bit. The acknowledge-bit is a HIGH signal put on SDA by the transmitter during the time when the master generates an extra acknowledge-related clock pulse. A slave receiver which is addressed must generate an acknowledge-bit after the reception of each byte. A master receiver must also generate an acknowledge-bit after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge-clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge-bit on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C Interface is illustrated as follows. Data output by Transmitter SCL from Master Data output by Receiver S START Condition 1 2 8 9 Clock pulse for acknowledgement Acknowledge Not acknowledge |
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