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SC7283 Datasheet(PDF) 46 Page - Sitronix Technology Co., Ltd. |
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SC7283 Datasheet(HTML) 46 Page - Sitronix Technology Co., Ltd. |
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46 / 89 page  SC7283 Version 1.0 Page 46 of 89 2018/11 7.3.4 Parallel 24 bit RGB Input Timing Table Parallel 24-bit RGB Input Timing (PVDD=VDD=VDDI= 3.3V, AGND= 0V, TA=25 C) 480RGB X 272 Resolution Timing Table Item Symbol Min. Typ. Max. Unit Remark DCLK Frequency Fclk 8 9 12 MHz DCLK Period Tclk 83 111 125 ns HSYNC Period Time Th 485 531 598 DCLK Display Period Thdisp 480 DCLK Back Porch Thbp 3 43 43 DCLK By H_BLANKING setting Front Porch Thfp 2 8 75 DCLK Pulse Width Thw 2 4 43 DCLK VSYNC Period Time Tv 276 292 321 HSYNC Display Period Tvdisp 272 HSYNC Back Porch Tvbp 2 12 12 HSYNC By V_BLANKING setting Front Porch Tvfp 2 8 37 HSYNC Pulse Width Tvw 2 4 12 HSYNC Note: It is necessary to keep Tvbp =12 and Thbp =43 in sync mode. DE mode is unnecessary to keep it. 7.3.5 Serial 8 bit RGB Input Timing Table Serial 8-bit RGB Input Timing (PVDD=VDD=VDDI= 3.3V, AGND= 0V, TA=25 C) 480RGB X 272 Resolution Timing Table Item Symbol Min. Typ. Max. Unit Remark DCLK Frequency Fclk 24 27 30 MHz DCLK Period Tclk 33 37 42 ns HSYNC Period Time Th 1445 1491 1558 DCLK Display Period Thdisp 1440 DCLK Back Porch Thbp 3 43 43 DCLK By H_BLANKING setting Front Porch Thfp 2 8 75 DCLK Pulse Width Thw 2 4 43 DCLK VSYNC Period Time Tv 276 292 321 HSYNC Display Period Tvdisp 272 HSYNC Back Porch Tvbp 2 12 12 HSYNC By V_BLANKING setting Front Porch Tvfp 2 8 37 HSYNC Pulse Width Tvw 2 4 12 HSYNC Note: It is necessary to keep Tvbp =12 and Thbp =43 in sync mode. DE mode is unnecessary to keep it. |
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