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AD7766 Datasheet(PDF) 7 Page - Analog Devices

Part # AD7766
Description  24-Bit, 10mW, 125ksps Analog to Digital Converter in 16 lead TSSOP
PDF  18 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7766 Datasheet(HTML) 7 Page - Analog Devices

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Preliminary Technical Data
AD7766
Rev. PrD | Page 7 of 18
TIMING SPECIFICATIONS
Table 3. AVDD = DVDD = 2.5 V ± 5%, VDRIVE = 1.7 V to 3.6 V, VREF = 5 V, TA = -40°C to +105°C, unless otherwise noted1
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DRDY Operation
t1
TBD
ns
DRDY Falling edge to MCLK rising edge
t2
TBD
ns
MCLK High Pulsewidth
t3
TBD
ns
MCLK Low Pulsewidth
t4
TBD
ns
MCLK Rising edge to DRDYRising edge
t5
TBD
ns
DRDY Pulse width
tREAD 2
tDRDY - t5
ns
DRDY low period. Read data during this period.
tDRDY2
n×8×tMCLK
ns
DRDY Period.
Read Operation
t6
0
ns
DRDY Falling Edge to CS Setup Time
t7
TBD
ns
CS Falling Edge to SDO three-state disabled
t8
TBD
ns
Data access time after SCLK falling edge
t9
TBD
ns
SCLK Falling Edge to Data Valid hold time
t10
TBD
ns
SCLK High Pulsewidth
t11
TBD
ns
SCLK Low Pulsewidth
t12
TBD
ns
Bus Relinquish Time after CS Rising Edge
t13
0
ns
CS Rising Edge to DRDY Rising Edge
Read Operation with CS low
t14
TBD
ns
DRDY Falling Edge to Data valid Setup Time
t15
0
ns
DRDY Rising Edge to Data Valid hold time
Daisy Chain Operation
t16
TBD
ns
SDI Valid to SCLK Falling Edge Setup Time
t17
TBD
ns
SCLK Falling Edge to SDI Valid Hold Time
Synchronise Operation
t18
TBD
ns
SYNC/PD Falling edge to MCLK Rising Edge
t19
TBD
ns
MCLK Rising edge to DRDY Rising Edge
t20
TBD
ns
SYNC/PD Rising edge to MCLK Rising Edge
t21
TBD
ns
MCLK Rising edge to DRDY Falling edge coming out of SYNC/PD
tSETTLING2
592×n +2
tMCLK
Filter Settling Time after a Reset or power down.
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of
1.6 V
2 n = 1 for AD7766, n= 2 for the AD7766-1, n=4 for the AD7766-2.



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