Preliminary Technical Data

AD7766

Rev. PrD | Page 9 of 18

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

3

AGND

6

SYNC/PD

7

CS

SDI

MCLK

SCLK

DRDY

16

15

14

13

12

DGND

SDO

11

10

9

REFGND

AD7766/

TOP VIEW

(Not to Scale)

AD7766-1/

AD7766-2

Figure 6.16-Lead TSSOP Pin Configuration

Table 5. Pin Function Descriptions

Pin

Number

Pin Mnemonic

Description

1

+2.5V Analog power supply.

2

Reference Input for the AD7766. An external reference must be applied to this input pin. The

VREF+ input can range from 2.4V to 5V. The reference voltage input is independent of the

3

REFGND

Reference Ground. Ground Connection for the reference voltage. The input reference voltage

4

Positive input of the Differential Analog input.

5

Negative input of the Differential Analog input.

6

AGND

Power supply ground for Analog circuitry.

7

SYNC/PD

Synchronisation and Power Down Input pin. This pin has dual functionality. It can be used to

synchronise multiple AD7766 devices and/or put the AD7766 device into power down mode.

See the Power Down, Reset & Synchronization section for further details.

8

DVDD

9

Logic power supply input, +1.8V to +3.6V. The voltage supplied at this pin will determine the

operating voltage of the digital logic interface.

10

SDO

Serial Data Output (SDO). The conversion result from the AD7766 is output on the SDO pin as a

24 bit, two’s complement, MSB first, serial data stream.

11

DGND

Digital logic power supply ground

12

DRDY

Data Ready Output. A falling edge on the DRDY signal indicates that a new conversion data

result is available in the output register of the AD7766. See the AD7766 Interface section for

further details.

13

SCLK

Serial Clock Input. The SCLK input provides the serial clock for all serial data transfers with the

AD7766 device. See the AD7766 Interface Section for further details.

14

MCLK

Master Clock Input. The AD7766 sampling frequency is directly proportional to the MCLK

frequency.

15

SDI

Serial Data Input. This is the Daisy-Chain input of the AD7766. See the

Daisy Chaining section for further details.

16

CS

Chip Select Input. The CS input selects the AD7766 device, and acts as an enable on the SDO

pin. In cases where CS is used, the MSB of the conversion result is clocked onto the SDO line on

the CS falling edge. The CS input allows multiple AD7766 devices to share the same SDO line.

This allows the user to select the appropriate device by supplying it with a logic low CS signal,

which enables the SDO pin of the device concerned. See the AD7766 Interface section for

further details.