Preliminary Technical Data

AD7766

AD7766 INTERFACE

The AD7766 provides the user with a flexible serial interface

enabling the user to implement the most desireable interfacing

scheme for their application. The AD7766 interface is

comprised of seven different signals. Five of these signals are

inputs : MCLK CS, SYNC/PD, SCLK, and SDI. There are two

output signals, DRDY and SDO.

INITIAL POWER-UP

On initial power up, apply a continuous MCLK signal. Iit is

recommended that the user reset the AD7766 to clear the filters

and ensure correct operation. The reset is completed as

described in Figure 5, with all events occurring relative to the

rising edge of MCLK. A negative pulse on the SYNC/PD input

initiates the reset and the DRDY output will switch to logic high

and will remain high until valid data is available.. Following the

power up of the AD7766 by transitioning the SYNC/PD pin to

logic high, a settling time is required before valid data is output

MCLK frequency and the decimation rate. Table 7 lists the

settling time of each of the AD7766 models, and should be

referenced to Figure 5..

Table 7. Filter settling time after SYNC/PD

Decimation Rate

AD7766

8

AD7766-1

16

AD7766-2

32

SYNC/PDto the falling edge of DRDY.

READING DATA

The AD7766 outputs its data conversion results in an MSB first,

2’s complement 24-bit format on the Serial Data Output Pin

(SDO). MCLK is the master clock, which controls all the

AD7766 conversions. The SCLK is the serial clock input for the

device. All data transfers take place with respect to the SCLK

signal

The DRDY line is used as a status signal to indicate when the

data is available to be read from the AD7766. The falling edge of

DRDY indicates that a new data word is available in the output

register of the device. DRDY stays low during the period that

output data is permitted to be read from the SDO pin. The

DRDY signal returns to logic high to indicate when not to read

from the device. Ensure that a data read is not attempted during

this period as the output register is being updated

The AD7766 offers the user the option of using a chip select

input signal (CS) in its data read cycle. The CS signal is a gate

for the SDO pin and allows many AD7766 devices to share the

same serial bus acting as an instruction signal to each of these

devices indicating permission to use the bus. When CS logic

high, the SDO line of the AD7766 is is tri-stated.

There are two distinct patterns that can be initiated to read data

from the AD7766 device, these are for the cases when CS falling

edge occurs after the DRDY falling edge and for the case when

the CS falling edge occurs before the DRDY falling edge (when

CS is set to logic low.

When the CS falling edge occurs after DRDY falling edge the

MSB of the conversion result is becomes available on the SDO

line on this CS falling edge. The remaining bits of the

conversion result (MSB-1, MSB-2 ..etc) are clocked onto the

SDO line by the falling edges of SCLK which follow the CS

falling edge. Figure 3 details this interfacing scheme.

When CS is tied low the AD7766 serial interface can operate in

3-wire mode as shown in Figure 4. In this case the MSB of the

conversion result is available on the SDO line on the falling

edge of DRDY. The remaining bits of the data conversion result

(MSB-1, MSB-2 etc..) are clocked onto the SDO line by the

subsequent SCLK falling edges.

POWER DOWN, RESET & SYNCHRONIZATION

The AD7766’s SYNC/PD pin allows the user to synchronise

multiple AD7766 devices. This pin also allows the user to reset

and power down the AD7766 device. These features are

implemented relative to the rising edges of MCLK and are

shown in Figure 5

To power down, reset or synchronise a device the AD7766

SYNC/PD pin should be taken low. On the first rising edge of

MCLK the AD7766 is powered down. The DRDY pin

transitions to logic high indicating that the data in the output

register is no longer valid. The status of the SYNC/PD pin is

checked on each subsequent rising edge of MCLK. On the first

rising edge of MCLK after the SYNC/PD pin is taken high the

AD7766 is taken out of power down. On the next rising edge,

the filter of the AD7766 is reset. On the following rising edge,

the first new sample is taken.

valid data is output by the device (as listed in Table 7). The

valid data is available on SDO for readback.