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AS6221T

Register Description

Datasheet

• PUBLIC

DS001032

• v1-00 • 2022-Apr-08

37

│ 23

Example 50 °C:

50°������/0.0078125°������ = 6400 = ������������������������������������ 0001 1001 0000 0000 = ������������������ 1900

Figure 28:

Temperature Conversion Examples

Temperature (°C)

Digital Output (Binary)

Digital Output (Hex)

60.0

0001 1110 0000 0000

1E00

50.0

0001 1001 0000 0000

1900

25.0

0000 1100 1000 0000

0C80

0.125

0000 0000 0001 0000

0010

0.0078125

0000 0000 0000 0001

0001

0.0

0000 0000 0000 0000

0000

6.3

Serial Interface

The device employs a standard I²C-serial bus.

6.3.1

Bus Description

A data transfer must be invoked by a master device (e.g. microcontroller) which defines the access to

the slave device. The master device defines and generates the serial clock (SCL) and the start/stop

conditions.

In order to address a specific device, a START condition has to be generated by the master device by

pulling the data line (SDA) from a logic high level to a logic low level while the serial clock signal (SCL)

is kept at high level.

After the start condition, the slave address byte is transmitted which is completed with a ninth bit which

indicates a read (bit=’1’) or a write operation (bit=’0’) respectively. All slaves read the data on the rising

edge of the clock. An acknowledge signal is generated by the addressed slave during the ninth clock

pulse. This acknowledge signal is produced by pulling the pin SDA to a low level by the selected

slave.

Subsequently, the byte data transfer is started and finished by an acknowledge bit. A change in the

data signal (SDA) while the clock signal (SCL) is high causes a START or STOP condition. Hence, it

must be ensured such a condition is prevented during a data transfer phase.

After completing the data transfer, the master generates a STOP condition by pulling the data line

(SDA) from low level to high level while the clock signal (SCL) is kept at high level.