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AS6221T Datasheet(PDF) 29 Page - ams AG |
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AS6221T Datasheet(HTML) 29 Page - ams AG |
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29 / 37 page ![]() Document Feedback AS6221T Register Description Datasheet • PUBLIC DS001032 • v1-00 • 2022-Apr-08 37 │ 29 Parameter Symbol Fast Mode High Speed Mode Unit Min Max Min Max Data setup time tSUDAT 100 10 ns SCL clock low period tLOW 1300 160 ns SCL clock high period tHIGH 600 60 ns Clock/Data fall time tF 300 80 ns Clock/Data rise time tR 300 80 ns Clock/Data rise time for SCL ≤100 kHz tR 1000 ns (1) The device will hold the SDA line high for 100 ns during the falling edge of the SCL. 6.3.15 Timing Diagrams The following timing diagrams depict the different bus operation modes and data transmission: Figure 33: Timing Diagram for Word Write 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SCL SDA 1 0 0 R /W 0 0 0 0 0 0 IX 1 IX 0 Start by master Values are defined by ADD 0 pin setting Frame 1: Slave Address Byte Frame 2: Index Register Byte 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SCL SDA Frame 3: MSB Data Byte Frame 4: LSB Data Byte D 7 D 6 D 5 D4 D 3 D 2 D 1 D 0 D 6 D5 D 4 D 3 D 2 D1 D 7 D0 (Continued ) (Continued ) Acknowledge by slave Acknowledge by slave Acknowledge by slave Acknowledge by slave Stop by master A3 A2 A1 A0 Values are defined by ALERT/ADD1 pin setting |
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