Document Feedback

AS6221T

Register Description

Datasheet

• PUBLIC

DS001032

• v1-00 • 2022-Apr-08

37

│ 25

ALERT / ADD1

Connection

ADD0 Connection

Alert

Functionality

Enabled

Device Address

(bin)

Device Address

(hex)

Pull up to VDD

SCL

Yes

100 1011

0x5B

6.3.4

Read/Write Operation

In order to access an internal data register, the index register must be written in advance. This register

contains the actual register address and selects the appropriate register for an access. A typical

transfer consists of the transmission of the slave address with a write operation indication, followed by

the transmission of the register address and is finalized with the actual register content data transfer.

This implies that every write operation to the temperature sensor device requires a value for the index

register prior to the transmission of the actual register data.

The index register defines the register address for both the write and read operation. Consequently, if

a read operation is executed, the register address is taken from the index register which was defined

from the last write operation.

If a different register needs to be read, the index register has to be written in advance to define the

new register address. This is accomplished by transmitting the slave address with a low R/W bit,

followed by the new content of the index register. Subsequently, the master provokes a START

condition on the bus and transmits the slave address with a high R/W bit in order to initiate a read

operation.

Since the index register always keeps its last value, reads can be executed repetitively on the same

register.

Similarly to the byte transfer where the MSB is transmitted first, the transfer of a 16-bit word is

executed by a two byte transfer whereas the MSB byte is always transmitted first.

6.3.5

Slave Operation

The device employs a slave functionality only (slave transmitter and slave receiver) and cannot be

operated as a bus master. Consequently, the device never actively drives the SCL line.

6.3.6

Slave Receiver Mode

Any transmission is invoked by the master device by transmitting the slave address with a low R/W bit.

Subsequently, the slave device acknowledges the reception of the valid address by pulling the ninth

bit to a low level. Following to acknowledge, the master transmits the content of the index register.

This transfer is again acknowledged by the slave device. The next data byte(s) are written to the

actual data register which is selected by the index register while each transfer is acknowledged upon a

completed transfer by the slave device. A data transfer can be finished if the master transmits a

START or a STOP condition on the bus.