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CS5467 Datasheet(PDF) 14 Page - Cirrus Logic

Part # CS5467
Description  Four-channel Power/Energy IC
PDF  46 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5467 Datasheet(HTML) 14 Page - Cirrus Logic

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CS5467
14
DS714A1
ADVANCE RELEASE
4. THEORY OF OPERATION
The CS5467 is a four-channel analog-to-digital convert-
er (ADC) followed by a computation engine that per-
forms
power
calculations
and
energy-to-pulse
conversion. The data flow for the voltage and current
channel measurement and the power calculation algo-
rithms are depicted in Figures 3, 4, and 5.
The CS5467 analog inputs are structured with two Cur-
rent
channels and two Voltage channels, and are opti-
mized to simplify interfacing to various sensing
elements. As shown in Figures 3 and 4, the current and
voltage channels are fully independent.
The voltage-sensing elements introduces a voltage
waveform on the two voltage channel inputs VIN
± and
VIN2
±, which is subject to a gain of 10x. A second-order
delta-sigma modulator samples the amplified signal for
digitization.
Simultaneously, the current-sensing elements introduce
a voltage waveform on the two current channel inputs
IIN
± and IIN2±, which is subject to the two selectable
gains of the programmable gain amplifier (PGA). The
amplified signals are sampled by a fourth-order
delta-sigma modulator for digitization. The converters
sample at a rate of MCLK/8. The over-sampling pro-
vides a wide dynamic range and simplified anti-alias fil-
ter design.
4.1 Digital Filters
The decimating digital filters on the four channels are
Sinc3 filters followed by 3rd-order IIR filters. The sin-
gle-bit data is passed to the low-pass decimation filter
and output at a fixed word rate. The output word is
passed to an IIR filter to compensate for the magnitude
roll off of the low-pass filtering operation.
An optional digital high-pass filter (HPF in Figures 3 and
4) removes any DC component from the selected signal
path. By removing the DC component from the voltage
and/or the current channel, any DC content will also be
removed from the calculated active power as well. With
both HPFs enabled the DC component will be removed
VOLTAGE
SINC3
+
X
Vgn
CURRENT
SINC3
+
X
I gn
DELAY
REG
I
DCoff
V
DCoff
PGA
+
+
Σ
Σ
Control Register
Digital Filter
Digital Filter
HPF
2nd Order
∆Σ
Modulator
4th Order
∆Σ
Modulator
x10
X
X
7
DELAY
REG
HPF
VQ
0
1
2
2322
...
X
X
X
Q
2
π
X
V
P
I
VHPF
IHPF
65
ε
APF
HPF
APF
IIR
3
...
Operational Modes Register
IIR
SYS
Gain
SYS
Gain
PC[6] PC[5] PC[4] PC[3] PC[2] PC[1] PC[0]
PC[7]
REGISTER NAMES INDICATED
IN SHADED AREAS.
IIR
Figure 3. Data Measurement Flow Diagram
2nd Order
∆Σ
Modulator
Control Register
+
X
V2gn
+
X
I2gn
I2
dcoff
V2
dcoff
PGA
+
+
Σ
Σ
HPF
4th Order
∆Σ
Modulator
HPF
V2Q
0
1
2
2322
...
X
X
X
Q2
π
X
V2
P2
I2
VHPF
IHPF
87
ε
APF
HPF
APF
3
CURRENT 2
...
Operational Modes Register
SINC3
SINC3
DELAY
REG
Digital Filter
Digital Filter
X
X
7
DELAY
REG
IIR
IIR
SYS
Gain
SYS
Gain
IIR
PC[6] PC[5] PC[4] PC[3] PC[2] PC[1] PC[0]
PC[7]
REGISTER NAMES INDICATED
IN SHADED AREAS.
X10
VOLTAGE 2
Figure 4. Data Measurement Flow Diagram



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