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CS5467 Datasheet(PDF) 20 Page - Cirrus Logic

Part # CS5467
Description  Four-channel Power/Energy IC
PDF  46 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5467 Datasheet(HTML) 20 Page - Cirrus Logic

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CS5467
20
DS714A1
ADVANCE RELEASE
rent registers. The maximum pulse frequency from the
E1 pin is (MCLK/K)/2048.
5.5.4 Voltage Channel Sign Mode
Setting bits E3MODE[1:0] = 2 (10b) in the Operational
Mode Register
outputs the sign of the voltage channel
on pin E3. Figure 8 illustrates the output format with volt-
age channel sign on E3
Output pin E3 is high when the line voltage is positive
and pin E3 is low when the line voltage is negative.
5.5.5 PFMON Output Mode
Setting bit E3MODE[1:0] = 1 (01b) in the Operational
Mode Register
outputs the state of the PFMON compar-
ator on pin E3. Figure 9 illustrates the output format with
PFMON on E3
When PFMON is greater than the threshold, pin E3 is
high and when PFMON is less than the threshold pin E3
is low.
5.6 Sag and Fault Detect Feature
Status bit VSAG (V2SAG) and IFAULT (I2FAULT) in the
Status Register,
indicates a sag occurred in the power
line voltage (voltage 2) and current (current 2), respec-
tively. For a sag condition to be identified, the absolute
value of the instantaneous voltage or current must be
less than the sag level for more than half of the sag du-
ration (see Figure 10).
To activate voltage sag detection, a voltage sag level
must be specified in the Voltage Sag Level Register
(VSAGlevel, V2SAGlevel), and a voltage sag duration
must be specified in the Voltage Sag Duration Register
(VSAGduration, V2SAGduration). To activate current fault
detection, a current sag level must be specified in the
Current Fault Level Register
(ISAGlevel, I2SAGlevel), and
a current sag duration must be specified in the Current
Fault Duration Register
(ISAGduration, I2SAGduration).
The voltage and current sag levels are specified as the
average of the absolute instantaneous voltage and cur-
rent, respectively. Voltage and current sag duration is
specified in terms of ADC cycles.
5.7 On-chip Temperature Sensor
The on-chip temperature sensor is designed to assist in
characterizing the measurement element over a desired
temperature range. Once a temperature characteriza-
tion is performed, the temperature sensor can be uti-
lized to assist in compensating for temperature drift.
Temperature measurements are performed when a one
is written to the Temperature Measurement (Tmeas) reg-
ister and stored in the Temperature Register. The Tem-
perature Register
(T) default is Celsius scale (°C). The
Temperature Gain Register
(Tgain) and Temperature
Offset Register
(Toff) are constant values allowing for
temperature scale conversions.
The temperature update rate is a function of the number
of ADC samples. With MCLK = 4.096 MHz and K = 1
the update rate is:
The Cycle Count Register (N) must be set to a value
greater than one. Status bit TUP in the Status Register,
indicates when the Temperature Register is updated.
The Temperature Offset Register sets the zero-degree
measurement. To improve temperature measurement
accuracy, the zero-degree offset may need to be adjust-
ed after the CS5467 is initialized. Temperature-offset
calibration is achieved by adjusting the Temperature
Offset Register
(Toff) by the differential temperature
(
∆T) measured from a calibrated digital thermometer
and the CS5467 temperature sensor. A one-degree ad-
justment to the Temperature Register (T) is achieved by
E3
E2
E1
Figure 8. Voltage Channel Sign Pulse outputs
E3
E2
E1
Above PFMON Threshold
Below PFMON Threshold
Figure 9. PFMON output to pin E3
Level
Duration
Figure 10. Sag and Fault Detect
2240 samples
MCLK K
⁄
() 1024
⁄
----------------------------------------
0.56 sec
=



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