CS5467 datasheet(17/46 Pages) CIRRUS

17 / 46 page

CS5467

DS714A1

ADVANCE RELEASE

5. FUNCTIONAL DESCRIPTION

5.1 Analog Inputs

The CS5467 is equipped with four fully differential input

channels. The inputs VIN

±, VIN2±, IIN±, and IIN2± are

designated as the voltage, voltage 2, current, and cur-

rent 2 channel inputs, respectively. The full-scale differ-

ential input voltage for the current and voltage channel

±250 mVP.

5.1.1 Voltage Channel Input

The output of the line voltage resistive divider or trans-

former is connected to the VIN+ (VIN2+) and VIN-

(VIN2-) input pins of the CS5467. The voltage channels

are equipped with a 10x fixed-gain amplifier. The

full-scale signal level that can be applied to the voltage

channel is

±250 mV. If the input signal is a sine wave,

the maximum RMS voltage at a gain 10x is:

which is approximately 70.7% of maximum peak volt-

age. The voltage channel is also equipped with a Volt-

age

Gain

allowing

for

additional

programmable gain of up to 4x.

5.1.2 Current Channel Inputs

The output of the current-sense resistor or transformer

is connected to the IIN+ (IIN2+) and IIN- (IIN2-) input

pins of the CS5467. To accommodate different cur-

rent-sensing elements, the current channel incorpo-

rates a programmable gain amplifier (PGA) with two

programmable input gains. Configuration Register bit

Igain (I2gain) defines the two gain selections and corre-

sponding maximum input signal level.

For example, if Igain=0 (I2gain=0), current channel 1(2)

PGA gain is set to 10x. If the input signals are pure si-

nusoids with zero phase shift, the maximum peak differ-

ential signal on the current or voltage channel is

±250 mVP. The input signal levels are approximately

70.7% of maximum peak voltage and produce a

full-scale energy pulse registration equal to 50% of ab-

solute maximum energy registration. This will be dis-

cussed further in See Section 5.5 Energy Pulse Output

on page 18.

The Current Gain Register also facilitates an additional

programmable gain of up to 4x. If an additional gain is

applied to the voltage and/or current channel, the maxi-

mum input range should be adjusted accordingly.

5.2 IIR Filters

The current and voltage channels are equipped with a

3rd-order IIR filter, that is used to compensate for the

magnitude roll off of the low-pass decimation filter.

5.3 High-pass Filters

By removing the offset from either channel, no error

component will be generated at DC when computing the

active power. By removing the offset from both chan-

nels, no error component will be generated at DC when

computing VRMS, IRMS, and apparent power. Operation-

al Mode Register

bits VHPF, VHPF2, IHPF and IHPF2

activate the HPF in the voltage and current channel, re-

spectively. When a high-pass filter is active in only one

channel, an all-pass filter (APF) is applied to the com-

panion channel. The APF has an amplitude response

that is flat within the channel bandwidth and is used for

matching phase in systems where only one HPF is en-

gaged.

5.4 Performing Measurements

The CS5467 performs measurements of instantaneous

voltage (Vn) and current (In), and calculates instanta-

neous power (Pn) at an output word rate (OWR) of

where K is the value of the clock divider selected in the

Configuration Register

by bits K[3:0]. Note that a value

of K[3:0] = 0000 results in a clock divider setting of 16,

rather than zero.

The RMS voltage (VRMS, V2RMS), RMS current (IRMS,

I2RMS), and active power (Pactive, P2active) are comput-

ed using N instantaneous samples of Vn, In, and Pn re-

spectively, where N is the value in the Cycle Count

and is referred to as a “computation cycle”. The

apparent power (S, S2) is the product of VRMS and IRMS.

A computation cycle is derived from the master clock

(MCLK), with frequency: Under default conditions and

with K = 1, N = 4000, and MCLK = 4.096 MHz – the

OWR = 4000 and the Computation Cycle = 1 Hz.

Igain, I2gain

Maximum Input

Gain

0±250 mV

10x

±50 mV

50x

Table 1. Current Channel PGA Setting

250mV

---------------------

176.78mV

RMS

≅

OWR

MCLK K

⁄

()

1024

-----------------------------

Computation Cycle

OWR

---------------

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