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CS5467 Datasheet(PDF) 25 Page - Cirrus Logic

Part # CS5467
Description  Four-channel Power/Energy IC
PDF  46 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5467 Datasheet(HTML) 25 Page - Cirrus Logic

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CS5467
DS714A1
25
ADVANCE RELEASE
5.15.4 Register Read/Write
The Read/Write informs the command decoder that a register access is required. During a read operation, the ad-
dressed register is loaded into the device’s output buffer and clocked out by SCLK. During a write operation, the
data is clocked into the input buffer and transferred to the addressed register upon completion of the 24th SCLK.
W/R
Write/Read control
0 = Read register
1 = Write register
RA[4:0]
Register address bits (bits 5 through 1) of the read/write command.
Page 0
Address
RA[4:0]
Name
Description
0
00000
Config
Configuration
1
00001
I
Instantaneous Current
2
00010
V
Instantaneous Voltage
3
00011
P
Instantaneous Power
4
00100
PActive
Average Active (Real) Power
5
00101
IRMS
RMS Current
6
00110
VRMS
RMS Voltage
7
00111
I2
Instantaneous Current 2
8
01000
V2
Instantaneous Voltage 2
9
01001
P2
Instantaneous Power 2
10
01010
P2Active
Average Active (Real) Power 2
11
01011
I2RMS
RMS Current 2
12
01100
V2RMS
RMS Voltage 2
13
01101
QAvg
Average Reactive Power
14
01110
Q
Instantaneous Reactive Power
15
01111
Status
Status (Write of ‘1’ to status bit will clear the bit)
16
10000
Q2Avg
Average Reactive Power 2
17
10001
Q2
Instantaneous Reactive Power 2
18
10010
Ipeak
Peak Current
19
10011
Vpeak
Peak Voltage
20
10100
S
Apparent Power
21
10101
PF
Power Factor
22
10110
I2peak
Peak Current 2
23
10111
V2peak
Peak Voltage 2
24
11000
S2
Apparent Power 2
25
11001
PF2
Power Factor 2
26
11010
Mask
Mask
27
11011
T
Temperature
28
11100
Ctrl
Control
29
11101
Ppulse
Active Energy Pulse Output Accumulator
30
11110
Spulse
Apparent Energy Pulse Output Accumulator
31
11111
Qpulse / Page
Reactive Energy Pulse Output Accumulator (read only)
and Page (write only)
Note: For proper operation, do not attempt to write to unspecified registers.
B7
B6
B5
B4
B3
B2
B1
B0
0W/R
RA4
RA3
RA2
RA1
RA0
0



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