56F8037 datasheet(104/180 Pages) FREESCALE

104 / 180 page

56F8037 Data Sheet, Rev. 2

104

Freescale Semiconductor

Preliminary

6.3.11.12 QSPI0 Clock Stop Disable (QSPI0_SD)—Bit 2

Each bit controls clocks to the indicated peripheral.

•

0 = The clock is disabled during Stop mode

•

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0

6.3.11.13 Reserved—Bit 1

This bit field is reserved. It must be set to 0.

6.3.11.14 PWM Clock Stop Disable (PWM_SD)—Bit 0

•

0 = The clock is disabled during Stop mode

•

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0

6.3.12

Stop Disable Register 1 (SD1)

See Section 6.3.11 for general information about Stop Disable Registers.

Figure 6-13 Stop Disable Register 1 (SD1)

6.3.12.1

Reserved—Bit 15

This bit field is reserved. It must be set to 0.

6.3.12.2

Programmable Interval Timer 2 Clock Stop Disable (PIT2_SD)—Bit 14

•

0 = The clock is disabled during Stop mode

•

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1

6.3.12.3

Programmable Interval Timer 1 Clock Stop Disable (PIT1_SD)—Bit 13

•

0 = The clock is disabled during Stop mode

•

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1

6.3.12.4

Programmable Interval Timer 0 Clock Stop Disable (PIT0_SD)—Bit 12

•

0 = The clock is disabled during Stop mode

•

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1

Base + $F

Read

PIT2_

PIT1_

PIT0_

TB3_

TB2_

TB1_

TB0_

TA3_

TA2_

TA1_

TA0_

Write

RESET

56F8037 Datasheet(PDF) 104 Page - Freescale Semiconductor, Inc

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