Note 7

Note 8

Note 9

Typicals are at 25 C and represent the most likely parametric norm

Note 10

Tested Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level)

Note 11

Design Limits are guaranteed but not 100% tested These limits are not used to calculate outgoing quality levels

Note 12

Pin Descriptions

Q Logic Inputs

These inputs program the Qs of the two

A B C D E

2nd-order bandpass filter stages Logic

(3 2 1 18 17)

AGND (4)

This is the analog and digital ground pin

and should be connected to the system

ground for split supply operation or bi-

ased to mid-supply for single supply op-

eration For best filter performance the

ground line should be ‘‘clean’’

V

These are the positive and negative

V

power supply inputs

Decoupling the

power supply pins with 01 mF or larger

capacitors is highly recommended

F1 IN (16)

These are the inputs to the bandpass fil-

F2 IN (5)

ter stages To minimize gain error the

source impedance should be less than 2

kX Input signals should be referenced

to AGND

F1 OUT (15)

These are the outputs of the bandpass

F2 OUT (6)

filter stages

A IN (13)

This is the inverting input to the uncom-

mitted operational amplifier The non-in-

verting input is internally connected to

AGND

A OUT (14)

This is the output of the uncommitted

operational amplifier

50100 (10)

This pin sets the ratio of the clock fre-

quency to the bandpass center frequen-

the ratio to 501

TTL CLK (7)

This is the TTL-level clock input pin

There are two logic threshold levels so

the MF8 can be operated on either sin-

gle-ended or split supplies with the logic

When this pin is not used (or when

CMOS logic levels are used) it should

CMOS CLK (8)

This pin is the input to a CMOS Schmitt

inverter Clock signals with CMOS logic

levels may be applied to this input If the

TTL input is used this pin should be con-

RC (9)

This pin allows the MF8 to generate its

own clock signal To do this connect an

external resistor between the RC pin and

the CMOS Clock input and an external

capacitor from the CMOS Clock input to

AGND The TTL Clock input should be

is driven from an external clock the RC

pin should be left open

10 Application Information

11 INTRODUCTION

A simplified block diagram for the MF8 is shown in

Figure 1

The analog signal path components are two identical 2nd-

order bandpass filters and an operational amplifier Each

filter has a fixed voltage gain of 2 The filters’ cutoff frequen-

cy is proportional to the clock frequency which may be ap-

plied to the chip from an external source or generated inter-

nally with the aid of an external resistor and capacitor The

100 depending on the logic level on pin 10 The ‘‘Q’’ of the

two filters can have any of 31 values ranging from 05 to 90

and is set by the logic levels on pins 1 2 3 17 and 18

Table I shows the available values of Q and the logic levels

required to obtain them The operational amplifier’s non-in-

verting input is internally grounded so it may be used only

for inverting applications

The components in the analog signal path can be intercon-

nected in several ways three of which are illustrated in

Fig-

ures 2a 2b and 2c The two second-order filter sections can

be used as separate filters whose center frequencies track

very closely as in

Figure 2a Each filter section has a high

input impedance and low output impedance The op amp

may be used for gain scaling or other inverting functions If

sharper cutoff slopes are desired the two filter sections

may be cascaded as in

Figure 2b Again the op amp is

uncommitted The circuit in

Figure 2c uses both filter sec-

tions with the op amp and three resistors to build a ‘‘multiple

feedback loop’’ filter This configuration offers the greatest

flexibility for fourth-order bandpass designs Virtually any

fourth-order all pole response shape (Butterworth Cheby-

shev) can be obtained with a wide range of bandwidths

simply by proper choice of resistor values and Q The three

connection schemes in

Figure 2 will be discussed in more

detail in Sections 14 and 15

4