MF8 datasheet(17/24 Pages) NSC

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10 Application Information (Continued)

tant but much greater flexibility and better performance will

be obtained by using the feedback techniques described in

16 INPUT IMPEDANCE

The input to each filter block is a switched-capacitor circuit

as shown in

Figure 14 During the first half of a clock cycle

the input capacitor charges to the input voltage Vin and

during the second half-cycle its charge is transferred to a

feedback capacitor The input impedance approximates a

resistor of value

Rin j

CinfCLK

Cin depends on the value of Q selected by the Q logic pins

and varies from about 1 pF to about 5 pF For a worst-case

calculation of Rin assume Cin e 5 pF Thus

Rin(min) j

5 c 10b12fCLK

TLH8694 – 22

FIGURE 14 Simplified MF8 Input Stage

At the maximum clock frequency of 1 MHz this gives

Rin j 200k Note that Rin increases as fCLK decreases so

the input impedance should never be less than this number

Source impedance should be low enough that the gain isn’t

significantly affected

17 OUTPUT DRIVE

The filter outputs can typically drivea5kX load resistor to

over g4V peak-to-peak Load resistors smaller than 5 kX

should not be used The operational amplifier can drive the

minimum recommended load resistance of 5 kX to at least

35V

18 SAMPLED-DATA SYSTEM CONSIDERATIONS

Aliasing

The MF8 is a sampled-data filter and as such differs in

many ways from conventional continuous-time filters An im-

portant characteristic of sampled-data systems is their ef-

fect on signals at frequencies greater than one-half the

sampling frequency (The MF8’s sampling frequency is the

same as its clock frequency) If a signal with a frequency

greater than one-half the sampling frequency is applied to

the input of a sampled-data system it will be ‘‘reflected’’ to

a frequency less than one-half the sampling frequency

Thus an input signal whose frequency is fs 2 a 10 Hz will

cause the system to respond as though the input frequency

was fs 2 b 10 Hz This phenomenon is known as ‘‘alias-

ing’’ Aliasing can be reduced or eliminated by limiting the

input signal spectrum to less than fs 2 This may in some

cases require the use of a bandwidth-limiting filter (a simple

passive RC network will generally suffice) ahead of the MF8

to attenuate unwanted high-frequency signals However

since the clock frequency is much greater than the center

frequency this will usually not be necessary

Output Steps

Another characteristic of sampled-data circuits is that the

output voltage changes only once every clock cycle result-

ing in a discontinuous output signal (

Figure 15 ) The ‘‘steps’’

are smaller when the clock-to-center-frequency ratio is

1001 than when the ratio is 501

Clock Frequency Limitations

The performance characteristics of a switched-capacitor fil-

ter depend on the switching (clock) frequency At very low

clock frequencies (below 10 Hz) the internal capacitors be-

gin to discharge slightly between clock cycles This is due to

very small parasitic leakage currents At very low clock fre-

quencies the time between clock cycles is relatively long

allowing the capacitors to discharge enough to affect the

filters’ output offset voltage and gain This effect becomes

stronger at elevated operating temperatures

At higher clock frequencies performance deviations are pri-

marily due to the reduced time available for the internal inte-

grating op amps to settle For this reason the clock wave-

form’s duty cycle should be as close as possible to 50%

especially at higher frequencies Filter Q shows more varia-

tion from the nominal values at higher frequencies as indi-

cated in the typical performance curves This is the reason

for the different maximum limits on Q accuracy at fCLK e

250 kHz and fCLK e 100 kHz in the table of performance

specifications

Center Frequency Accuracy

Ideally the ratio fCLK f0 should be precisely 100 or 50 de-

pending on the logic voltage on pin 10 However as Table I

shows this ratio will change slightly depending on the Q

selected As the table shows the largest errors occur at the

lowest values of Q

TLH8694 – 23

FIGURE 15 Output Waveform of

MF8 Showing Sampling Steps

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