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MP5981 Datasheet(PDF) 17 Page - Monolithic Power Systems

Part # MP5981
Description  16V, 50A, 1.1mΩ RDS(ON),Hot-Swap Intelli-Fuse Solution
PDF  27 Pages
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP5981 Datasheet(HTML) 17 Page - Monolithic Power Systems

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MP5981
– 16V, 50A, 1.1mΩ RDS(ON), HOT-SWAP INTELLI-FUSE SOLUTION
MP5981 Rev. 1.3
MonolithicPower.com
17
5/16/2022
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
t
VIN
VGS
VOUT
3.3V
VDD3
MP5981 UVLO
GOK
ON/PD
CLREF
VCLREF_SS
e.g. 500 mV
VCLREF_NORM
e.g. 1.4V
Inse rtio n Dela y
On Delay
Determined
by Controlle r
>1.4V
VCS
Figure 4: Start-Up when the MP5981 is
Controlled by a Hot-Swap Controller
If the MP5981 works in standalone mode, an
external capacitor (CON) can be connected from
ON/PD to ground for an automatic start-up (see
Figure 5). The internal 4.2µA current source
charges the capacitor when VDD3 exceeds the
UVLO. ON/PD can also be pulled up externally
to the VDD3 voltage. A 10µA CLREF current
source
determines
the
current
limit
level
through a resistor to ground.
VIN
VOUT
MP5981
VIN
VOUT
CS
IMON
ON/PD
VDD3
CLREF
VTEMP
SS
GOK
GND
D_OC
RIMON
RCS
RCLREF
CON
CSS
TVS
Figure 5: MP5981 Schematic when Operating in
Standalone Mode
Once the ON/PD voltage exceeds 1.4V and the
insertion delay time ends, the power FET is
charged up by the internal 12
μA charge pump.
The power FET turns on when VGS reaches
VGSTH, and then the output voltage rises. The
current-limit
reference
voltage
is
clamped
internally to different voltage levels according to
VOUT. The external CLREF voltage is higher
than the internal VBE clamp (see Figure 6).
If the external CLREF voltage is below the
clamp voltage, the actual current limit reference
is determined by the CLREF voltage.
t
VIN
VGS
VOUT
3.3V
VDD3
MP5981 UVLO
GOK
ON/PD
CLREF
Insertion Delay
1.4V
VBE
80% of VIN
1.6V
VCS
VCLREF_NORM
Figure 6: Start-Up when the MP5981 Operates
in Standalone Mode
Soft Start (SS)
A capacitor connected to SS determines the
soft-start time. When ON/PD is pulled high and
the insertion delay time ends, a constant
current source proportional to the input voltage
charges up the SS voltage. The output voltage
rises at a similar slew rate to the SS voltage.
The SS capacitor value can be calculated with
Equation (3):
SS
SS
SS
R
t
9
C
=
(3)
Where tSS is the soft-start time (ms), CSS is the
soft-start capacitor (nF), and RSS is 0.8MΩ.
For example, a 100nF capacitor provides a soft-
start time of 8.89ms. If the load capacitance is
extremely
large,
the
current
required
to
maintain the preset soft-start time exceeds the
start-up current limit. In this case, the rise time
is controlled by the load capacitor and the start-
up current limit. Float SS to generate a fast
ramp-up voltage. A 12
μA current source pulls
up the gate of the power FET. The gate charge
current controls the output voltage rise time.
The approximate soft-start time is then 1.5ms,
which is the minimum output voltage soft-start
time.
ON/PD Control
ON/PD can be used for on/off control of the
power FET and the pull-down mode of the
output voltage. There are three types of
connection on ON/PD:



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