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MP5981 Datasheet(PDF) 5 Page - Monolithic Power Systems

Part # MP5981
Description  16V, 50A, 1.1mΩ RDS(ON),Hot-Swap Intelli-Fuse Solution
PDF  27 Pages
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP5981 Datasheet(HTML) 5 Page - Monolithic Power Systems

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MP5981
– 16V, 50A, 1.1mΩ RDS(ON), HOT-SWAP INTELLI-FUSE SOLUTION
MP5981 Rev. 1.3
MonolithicPower.com
5
5/16/2022
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
PIN FUNCTIONS
Pin #
Name
Description
9-16
VIN
System input power supply. The MP5981 operates from a 4V to 16V input rail.
1, 2,
25-32
VOUT
Output voltage controlled by the IC. VOUT is connected to the source of the integrated
MOSFET.
3
D_OC
Digital output of the over-current indication. D_OC is an open-drain output. When the
CS voltage (VCS) is higher than 85% of CLREF, the D_OC logic is pulled low.
4
ON/PD
Power FET on/off control and VOUT pull-down mode control. Drive ON/PD between
1.4V and 3V to turn the power FET on; drive ON/PD low to turn the power FET off. Do not
float ON/PD. To pull down VOUT after a 2.1ms delay, use an integrated
500Ω resistor to
force ON/PD to about 1V. If the MP5981 is controlled by the hot-swap controller, connect
a 10k
Ω resistor from ON/PD to GND.
5
GOK
Intelli-Fuse fault reporting output. GOK asserts low and latches after a fault occurs.
The faults that can trigger GOK include over-current fault (during normal operation), short-
circuit fault, over-temperature fault, and FET health fault. GOK is an open-drain output
pin.
6, 7
NC
No connection.
8
MODE
Latch or hiccup operation. If the mode pin is pulled to GND, the MP5981 operates in
hiccup mode and automatically retries after ~560ms. The MODE pin has an internal pull
up, and if not pulled low externally will default to latch mode operation.
17
NC
No connection. Connect this pin to GND.
18
VTEMP
Junction temperature sense output.
19
SS
Soft-start set. An external capacitor connected to SS sets the soft-start time of the output
voltage. The internal circuit controls the slew rate of the output voltage during turn-on.
20
GND
Signal ground.
21
VDD3
Internal 3.0V LDO output. VDD3 can be driven with an external 3.3V to reduce loss from
VIN. Place a 1µF decoupling capacitor close to VDD3 and GND.
22
IMON
Current monitor output. The output current is proportional to the current flowing through
the power device.
23
CS
Current-sense output. CS requires an external resistor. The CS voltage (VCS) is
compared with CLREF to determine the current limit.
24
CLREF
Current-limit reference voltage input.
ABSOLUTE MAXIMUM RATINGS (1)
VIN (DC) .......................................-0.3V to +20V
VIN (1
μs).................................................... +24V
VIN (25ns).................................................. +29V
VOUT ............................................-0.3V to +20V
All other pins ................................-0.3V to +4.2V
Continuous power dissipation (TA = 25°C) (2)
................................................................. 5.34W
Junction temperature ................................150°C
Lead temperature .....................................260°C
Storage temperature ................ -65°C to +155°C
Recommended Operating Conditions (3)
Input voltage operating range ............. 4V to 16V
Operating junction temp (TJ) .... -40°C to +125°C
Thermal Resistance (4)
θJA
θJC
LGA-32 (5mmx5mm) ............ 23.4 ....12.5 . °C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-to-
ambient thermal resistance θ
JA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX) - TA) / θJA. Exceeding the maximum allowable power
dissipation produces an excessive die temperature, causing
the regulator to go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.



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