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RT5510WSC Datasheet(PDF) 32 Page - Richtek Technology Corporation |
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RT5510WSC Datasheet(HTML) 32 Page - Richtek Technology Corporation |
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32 / 52 page ![]() RT5510 Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation www.richtek.com DS5510-00 October 2019 32 The maximum power dissipation depends on the operating ambient temperature for the fixed TJ(MAX) and the thermal resistance, JA. The derating curves in Figure 27 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. Figure 27. Derating Curve of Maximum Power Dissipation Layout Considerations For the best performance of the RT5510, the below PCB layout guidelines including the below items must be strictly followed. VBAT connect to LX through the boost inductor. Place the inductor as close as possible to the chip with 80 mil width at least. The shorter and wider trace provides lower parasitic inductance and resistance for achieving better efficiency. The VBAT pin only consumes few micro amperes for internal analog circuit, so the trace with 6 mil width is enough for VBAT of the RT5510. The VBAT capacitor handling high noisy current for boost circuit, please connect it to BGND and PGND first for shorten the current path and minimize the influence to digital circuit. LBST Boost Inductor 25*20mm r Main Ground BGND & PGND CINB 10µF/10V 0805 TOP 2nd Layer GND 3rd Layer Main Ground Bottom VBAT VBAT BCK LRCK DATAO WDT/ ADS2 LX LX BGND DATAI SCL DGND RSTN SDA VSNSN VSNSP AGND VREF ADS1 PGND PGND OUTP VBST OUTN PVDD PVDD VBST A B C D E F BGND VBAT IOVDD DVDD BGND & PGND INT CVBAT 0.1µF/10V 0402 CPVDD PVDD Cap 22µF/25V 0805 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 25 50 75 100 125 Ambient Temperature (°C) Four-Layer PCB |
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